Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.

Abstract: A thin film transistor includes an oxide semiconductor layer including a channel region, and a source region and a drain region having a resistivity lower than that of the channel region; a gate insulating layer disposed on the channel region of the oxide semiconductor layer; a gate electrode disposed on the gate insulating layer; and an aluminum oxide layer covering the lateral surface of the gate insulating layer, and the source region and the drain region, wherein the gate insulating layer has a multi-layer structure including a first insulating layer and a second insulating layer, and the first insulating layer contains silicon oxide as a main component, and is disposed on and in contact with the channel region.

Abstract: A thin-film transistor (TFT) substrate is provided which includes: a substrate; a TFT disposed above the substrate; and a capacitor disposed above the substrate and electrically connected with the TFT, wherein the capacitor includes: a lower electrode layer disposed above the substrate and including an electrically conductive material as a main component; an upper electrode layer disposed above and opposed to the lower electrode layer and including, as a main component, an oxide semiconductor material to which electrical conductivity is given; and a capacitor insulating layer disposed between the lower electrode layer and the upper electrode layer. An extension extending outward from at least a portion of the outer edge of the lower electrode layer in plan view is provided to the lower electrode layer. In plan view, the upper electrode layer covers the lower electrode layer except the extension.

Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.

Abstract: A thin-film transistor (TFT) substrate is provided which includes: a substrate; a TFT disposed above the substrate; and a capacitor disposed above the substrate and electrically connected with the TFT, wherein the capacitor includes: a lower electrode layer disposed above the substrate and including an electrically conductive material as a main component; an upper electrode layer disposed above and opposed to the lower electrode layer and including, as a main component, an oxide semiconductor material to which electrical conductivity is given; and a capacitor insulating layer disposed between the lower electrode layer and the upper electrode layer. An extension extending outward from at least a portion of the outer edge of the lower electrode layer in plan view is provided to the lower electrode layer. In plan view, the upper electrode layer covers the lower electrode layer except the extension.

Abstract: A thin film transistor includes an oxide semiconductor layer including a channel region, and a source region and a drain region having a resistivity lower than that of the channel region; a gate insulating layer disposed on the channel region of the oxide semiconductor layer; a gate electrode disposed on the gate insulating layer; and an aluminum oxide layer covering the lateral surface of the gate insulating layer, and the source region and the drain region, wherein the gate insulating layer has a multi-layer structure including a first insulating layer and a second insulating layer, and the first insulating layer contains silicon oxide as a main component, and is disposed on and in contact with the channel region.

Abstract: A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor includes: forming a planarization layer comprising polyimide material above the thin-film transistor; and heating the thin-film transistor at a temperature of 240° C. or lower after the planarization layer is formed.

Abstract: A thin-film transistor includes: a gate electrode; a channel layer not adjacent to the gate electrode; a channel protection layer exposing portion of the channel layer, a source electrode contacting the channel layer at portion of an exposed portion of the channel layer, and a drain electrode contacting the channel layer at portion of the exposed portion, in respective order. The channel layer includes oxide semiconductor. Surface of the channel protection layer includes upper surface and side surface extending from the upper surface to the exposed portion. The drain electrode has: a rising portion extending from above the exposed region to the channel layer along the side surface; and an upper surface covering portion continuous with the rising portion and extending onto portion of the upper surface. The upper surface covering portion has a facing portion facing a channel region and being 2.5 ?m or less in channel length direction.

Abstract: A thin-film transistor includes: a gate electrode; a channel layer not adjacent to the gate electrode; a channel protection layer exposing portion of the channel layer; a source electrode contacting the channel layer at portion of an exposed portion of the channel layer; and a drain electrode contacting the channel layer at portion of the exposed portion, in respective order. The channel layer includes oxide semiconductor. Surface of the channel protection layer includes upper surface and side surface extending from the upper surface to the exposed portion. The drain electrode has: a rising portion extending from above the exposed region to the channel layer along the side surface; and an upper surface covering portion continuous with the rising portion and extending onto portion of the upper surface. The upper surface covering portion has a facing portion facing a channel region and being 2.5 ?m or less in channel length direction.

Abstract: A thin film semiconductor device comprises a substrate, a gate electrode disposed above the substrate, an oxide semiconductor layer disposed above the substrate so as to oppose the gate electrode, a channel protective layer disposed on the oxide semiconductor layer, and a source electrode and a drain electrode each connected to the oxide semiconductor layer. The density of states DOS [eV?1cm?3] of oxygen defects in the oxide semiconductor layer satisfies the following relationship: DOS?1.710×1017×(Ec?E)2?6.468×1017×(Ec?E)+6.113×1017 provided that 2.0 eV?Ec?E?2.7 eV where Ec [eV] is an energy level of a conduction band edge of the oxide semiconductor layer and E [eV] is a predetermined energy level of the oxide semiconductor layer.

Abstract: A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor includes: forming a planarization layer comprising polyimide material above the thin-film transistor; and heating the thin-film transistor at a temperature of 240° C. or lower after the planarization layer is formed.

Abstract: A thin film semiconductor device comprises a substrate, a gate electrode disposed above the substrate, an oxide semiconductor layer disposed above the substrate so as to oppose the gate electrode, a channel protective layer disposed on the oxide semiconductor layer, and a source electrode and a drain electrode each connected to the oxide semiconductor layer. The density of states DOS [eV?1cm?3] of oxygen defects in the oxide semiconductor layer satisfies the following relationship: DOS?1.710×1017×(Ec?E)2?6.468×1017×(Ec?E)+6.113×1017 provided that 2.0 eV?Ec?E?2.7 eV where Ec [eV] is an energy level of a conduction band edge of the oxide semiconductor layer and E [eV] is a predetermined energy level of the oxide semiconductor layer.

Abstract: A structure of a panel which can be thinned down to about a panel thickness of a PDP and a manufacturing method thereof are provided. A gas filling hole is provided to a surface of a rear glass substrate of a PDP, the surface coming in contact with a front glass substrate of the PDP. Vacuuming and filling of a discharge gas are performed through the gas filling hole. After filling of the discharge gas, a mechanism for lifting solder iron up and down and supplying solder provided inside a chamber inserts a tip of an ultrasonic soldering iron into the gas filling hole to start supplying a solder which is a material for a plug sealant. When a series of forming steps of the plug sealant are finished, the ultrasonic soldering iron is retreated before the solder is solidified to finish formation of the plug sealant.

Abstract: A structure of a panel which can be thinned down to about a panel thickness of a PDP and a manufacturing method thereof are provided. A gas filling hole is provided to a surface of a rear glass substrate of a PDP, the surface coming in contact with a front glass substrate of the PDP. Vacuuming and filling of a discharge gas are performed through the gas filling hole. After filling of the discharge gas, a mechanism for lifting solder iron up and down and supplying solder provided inside a chamber inserts a tip of an ultrasonic soldering iron into the gas filling hole to start supplying a solder which is a material for a plug sealant. When a series of forming steps of the plug sealant are finished, the ultrasonic soldering iron is retreated before the solder is solidified to finish formation of the plug sealant.

Abstract: A method of manufacturing a display panel in which a sealing layer is formed so as to enclose an internal space created between a pair of opposite front and back substrates, and the sealing material is heated to soften at a predetermined temperature and fuse to the substrates to seal the internal space. A primary evacuation process for evacuation of the discharge space and an introduction process for introducing replacement gas into the discharge space undergoing the primary evacuation process are performed after a temperature for heating the sealing layer reaches a starting temperature for softening the sealing layer and before the sealing process for sealing the discharge space with the sealing layer is performed.

Abstract: A method of manufacturing a display panel in which a sealing layer is formed so as to enclose an internal space created between a pair of opposite front and back substrates, and the sealing material is heated to soften at a predetermined temperature and fuse to the substrates to seal the internal space. A primary evacuation process for evacuation of the discharge space and an introduction process for introducing replacement gas into the discharge space undergoing the primary evacuation process are performed after a temperature for heating the sealing layer reaches a starting temperature for softening the sealing layer and before the sealing process for sealing the discharge space with the sealing layer is performed.