Patents by Inventor Toshie Kato

Toshie Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Input/output circuit and system
    Patent number: 8497709
    Abstract: An input/output circuit has a first load having one end coupled to a first standard voltage line, a first MOS transistor having a drain electrode coupled to another end of the first load, a second load having one end coupled to the first standard voltage line, a second MOS transistor having a drain electrode coupled to another end of the second load, a third MOS transistor having a source electrode each of which is coupled to source electrodes of the first and second MOS transistors, a first constant-current source coupled between the source electrode of the first MOS transistor and a second standard voltage line, and a second constant-current source coupled between the source electrode of the second MOS transistor and the second standard voltage line. The circuit size is reduced by transmitting a differential signal or a single-ended signal using a single input/output circuit.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Norihiko Fukuzumi, Toshie Kato
  • INPUT/OUTPUT CIRCUIT AND SYSTEM
    Publication number: 20110279167
    Abstract: An input/output circuit has a first load having one end coupled to a first standard voltage line, a first MOS transistor having a drain electrode coupled to another end of the first load, a second load having one end coupled to the first standard voltage line, a second MOS transistor having a drain electrode coupled to another end of the second load, a third MOS transistor having a source electrode each of which is coupled to source electrodes of the first and second MOS transistors, a first constant-current source coupled between the source electrode of the first MOS transistor and a second standard voltage line, and a second constant-current source coupled between the source electrode of the second MOS transistor and the second standard voltage line. The circuit size is reduced by transmitting a differential signal or a single-ended signal using a single input/output circuit.
    Type: Application
    Filed: January 28, 2011
    Publication date: November 17, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Norihiko Fukuzumi, Toshie Kato