Patents by Inventor Toshiharu Seko

Toshiharu Seko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130058074
    Abstract: A handrail with an illumination function includes: a handrail main body; a decorative cover that is disposed at part of the handrail main body so as to extend along a longitudinal direction of the handrail main body and has a light transmitting property; a flatter that is disposed on an inner side with respect to the decorative cover so as to extend along the longitudinal direction of the handrail main body and reflects and diffuses light to radiate the light through a slit; and a light source that is disposed on an inner side of the flatter.
    Type: Application
    Filed: July 27, 2012
    Publication date: March 7, 2013
    Inventors: Junichi SOMEI, Toshiharu Seko
  • Patent number: 7977805
    Abstract: A flexible wiring substrate is provided which realizes a fine pitch of a wiring pattern and improves mechanical strength of the wiring pattern so as to prevent breaks or exfoliation of the wiring pattern. A flexible wiring substrate 3 of the present invention includes an insulation tape 6, and a wiring pattern 7 formed on the insulation tape 6. A thickness of the wiring pattern 7 is made thinner in a mounting region, where a semiconductor element is connected to, than in a non-mounting region.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: July 12, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko
  • Patent number: 7750457
    Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: July 6, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko
  • Patent number: 7671454
    Abstract: A tape carrier of the present invention includes an insulating tape and a wiring pattern formed on the insulating tape. The wiring pattern includes a connecting section via which the wiring pattern is connected to a bump electrode. The connecting section is provided at a part of an overlap part of the wiring pattern, which overlap part overlaps a semiconductor device when the semiconductor device is mounted on the wiring pattern. The connecting section of the wiring pattern is smaller in wiring width than the remaining part of the overlap part, which remaining part is other than the connecting section.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: March 2, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko
  • Patent number: 7582976
    Abstract: The present invention provides a semiconductor device tape carrier formed of an insulative tape 1 of a thin film, which becomes a semiconductor device by conducting a plurality of wire patterns 11 on its surface to a bump 23 of a semiconductor element 21 and being sealed by an insulative resin 22, wherein: an outer dimension of the semiconductor device in a carriage direction of the insulative tape 1 is greater than an integral multiple X (X=1, 2, 3, 4, 5, . . . ) of a pitch interval of sprocket holes 2, which are openings formed to carry the insulative tape 1, and not more than: the integral multiple X+a decimal Y (0<Y<1), and the tape pitch for a single semiconductor device is set to the integral multiple X+a decimal Y (0<Y<1).
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: September 1, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiharu Seko, Kenji Toyosawa
  • Patent number: 7466030
    Abstract: The semiconductor device uses an insulating resin that contains at least a resin anti-repellent for adjusting wettability of the insulating resin. The insulating resin is applied on a circuit board, and a semiconductor element is placed thereon and pressed against it. The applied pressure pushes out a portion of the insulating resin under the semiconductor element. This portion of the insulating resin combines with a portion of the insulating resin around the semiconductor element to form a resin fillet on the side surfaces of the semiconductor element.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 16, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko
  • Publication number: 20080251946
    Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.
    Type: Application
    Filed: February 7, 2008
    Publication date: October 16, 2008
    Inventor: Toshiharu Seko
  • Publication number: 20080061432
    Abstract: The present invention provides a semiconductor device tape carrier formed of an insulative tape 1 of a thin film, which becomes a semiconductor device by conducting a plurality of wire patterns 11 on its surface to a bump 23 of a semiconductor element 21 and being sealed by an insulative resin 22, wherein: an outer dimension of the semiconductor device in a carriage direction of the insulative tape 1 is greater than an integral multiple X (X=1, 2, 3, 4, 5, . . . ) of a pitch interval of sprocket holes 2, which are openings formed to carry the insulative tape 1, and not more than: the integral multiple X+a decimal Y (0?Y?1), and the tape pitch for a single semiconductor device is set to the integral multiple X+a decimal Y (0?Y?1).
    Type: Application
    Filed: September 6, 2007
    Publication date: March 13, 2008
    Inventors: Toshiharu Seko, Kenji Toyosawa
  • Patent number: 7304394
    Abstract: A wiring pattern is provided on an insulating tape. Part of the wiring pattern is a connection section. An insulating resin is provided so that the connection section is coated with the insulating resin. A protrusion electrode of a semiconductor element is so positioned on the connection section so that the protrusion electrode will push away the insulating resin and be connected with the connection section. Then, the semiconductor is pressed in Direction D1. Heat is applied while pressing in Direction D1. In this way, the connection section intrudes into the protrusion electrode, thereby causing the connection section and the protrusion electrode to be connected with each other.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: December 4, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko
  • Publication number: 20070262425
    Abstract: A tape carrier of the present invention includes an insulating tape and a wiring pattern formed on the insulating tape. The wiring pattern includes a connecting section via which the wiring pattern is connected to a bump electrode. The connecting section is provided at a part of an overlap part of the wiring pattern, which overlap part overlaps a semiconductor device when the semiconductor device is mounted on the wiring pattern. The connecting section of the wiring pattern is smaller in wiring width than the remaining part of the overlap part, which remaining part is other than the connecting section.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 15, 2007
    Inventor: Toshiharu Seko
  • Patent number: 7053494
    Abstract: A semiconductor device includes a film substrate having an interconnection pattern provided on a surface thereof, a semiconductor chip mounted on the film substrate and having an electrode provided on a surface thereof, and an insulative resin portion provided between the film substrate and the semiconductor chip, the resin portion having been formed by applying an insulative resin on at least one of the film substrate and the semiconductor chip and filling a space defined between the film substrate and the semiconductor chip with the resin when the semiconductor chip is mounted on the film substrate, wherein the interconnection pattern has a projection which has a sectional shape tapered toward the electrode of the semiconductor chip and intrudes in the electrode thereby to be electrically connected to the electrode.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: May 30, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko
  • Publication number: 20060097368
    Abstract: A flexible wiring substrate is provided which realizes a fine pitch of a wiring pattern and improves mechanical strength of the wiring pattern so as to prevent breaks or exfoliation of the wiring pattern. A flexible wiring substrate 3 of the present invention includes an insulation tape 6, and a wiring pattern 7 formed on the insulation tape 6. A thickness of the wiring pattern 7 is made thinner in a mounting region, where a semiconductor element is connected to, than in a non-mounting region.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 11, 2006
    Inventor: Toshiharu Seko
  • Publication number: 20050224939
    Abstract: As illustrated in FIG. 2(a), a wiring pattern 2 is provided on an insulating tape 1. Part of the wiring pattern 2 is a connection section 4 for connection. As illustrated in FIG. 2(b), an insulating resin 7 is provided so that the connection section 4 is coated with the insulating resin 7. As illustrated in FIG. 2(c), a protrusion electrode 6 of a semiconductor element 3 is so positioned on the connection section 4 so that the protrusion electrode 6 will push away the insulating resin 7 and be connected with the connection section. Then, the semiconductor is pressed in Direction D1. As illustrated in FIG. 2(d), heat is applied while pressing in Direction D1. In this way, the connection section 4 intrudes into the protrusion electrode 6, thereby causing the connection section 4 and the protrusion electrode 6 to be connected with each other. With this, it is possible to provide a COF semiconductor device having better bonding strength between the tape and the semiconductor element.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 13, 2005
    Inventor: Toshiharu Seko
  • Publication number: 20050218513
    Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.
    Type: Application
    Filed: March 29, 2005
    Publication date: October 6, 2005
    Inventor: Toshiharu Seko
  • Patent number: 6864119
    Abstract: A manufacturing method for a COF semiconductor device according to the present invention comprises: Step (A) of applying an insulating resin composition to a surface of an insulating tape on the surface of which a plurality of wiring patterns is arranged; Step (B) of pressably contacting a semiconductor element to the wiring patterns in the condition wherein the insulating resin composition is not yet cured; and Step (C) of fixing the semiconductor element to the wiring patterns so as to be electrically connected by curing the insulating resin composition, wherein the manufacturing method for a COF semiconductor device further includes Step (D) of pre-heating the insulating tape from the rear surface side before, during, and/or after the application of the insulating resin composition.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: March 8, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko
  • Publication number: 20040227256
    Abstract: A semiconductor device includes a film substrate having an interconnection pattern provided on a surface thereof, a semiconductor chip mounted on the film substrate and having an electrode provided on a surface thereof, and an insulative resin portion provided between the film substrate and the semiconductor chip, the resin portion having been formed by applying an insulative resin on at least one of the film substrate and the semiconductor chip and filling a space defined between the film substrate and the semiconductor chip with the resin when the semiconductor chip is mounted on the film substrate, wherein the interconnection pattern has a projection which has a sectional shape tapered toward the electrode of the semiconductor chip and intrudes in the electrode thereby to be electrically connected to the electrode.
    Type: Application
    Filed: May 6, 2004
    Publication date: November 18, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Toshiharu Seko
  • Publication number: 20040061240
    Abstract: The semiconductor device uses an insulating resin that contains at least a resin anti-repellent for adjusting wettability of the insulating resin. The insulating resin is applied on a circuit board, and a semiconductor element is placed thereon and pressed against it. The applied pressure pushes out a portion of the insulating resin under the semiconductor element. This portion of the insulating resin combines with a portion of the insulating resin around the semiconductor element to form a resin fillet on the side surfaces of the semiconductor element.
    Type: Application
    Filed: September 24, 2003
    Publication date: April 1, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Toshiharu Seko
  • Publication number: 20040063332
    Abstract: A manufacturing method for a COF semiconductor device according to the present invention comprises:
    Type: Application
    Filed: September 24, 2003
    Publication date: April 1, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Toshiharu Seko
  • Patent number: 6710458
    Abstract: A dummy pattern for preventing generation of air bubbles in resin sealing of a semiconductor element is provided at a corner of the semiconductor element on a tape carrier which is composed of a polyimide-based insulating tape and a copper foil pattern formed thereon. The dummy pattern makes it possible to control flow of sealing resin from the corner of the semiconductor element to a space between a lower surface of the semiconductor element and the insulating tape, resulting in prevention of air bubbles generated in resin sealing of the semiconductor element. A generation rate of air bubble can be decreased to 50% or less as compared with a conventional COF semiconductor device.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: March 23, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko
  • Patent number: 6559524
    Abstract: A COF-use tape carrier for a semiconductor device has dummy leads not to be electrically connected to a semiconductor chip, in the proximity of an edge of an opening of a solder resist. The dummy leads are provided on an insulating tape, between adjacent two inner leads that are relatively widely spaced from each other. The dummy leads extend across the edge of the opening of the solder resist, so that one end of each dummy lead is located within the opening of the solder resist, while the other end of the dummy lead is located under the solder resist. A semiconductor chip is to be mounted on a chip-mounting region of the insulating tape.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: May 6, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshiharu Seko