Abstract: A plasma processing apparatus includes: a chamber; a substrate support including a lower electrode; an upper electrode disposed above the substrate support; a first RF power supply that is electrically connected to the upper electrode and generates a first RF signal, in which the first RF signal has a first power level during a first state within a repeating period and a zero power level during second to fourth states within the repeating period; a second RF power supply that is electrically connected to the lower electrode and generates a second RF signal, in which the second RF signal has a zero power level during the first and second states, a second power level during the third state, and a third power level during the fourth state; and a DC power supply that is electrically connected to the upper electrode and generates a DC signal.

Abstract: Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

Abstract: A substrate is provided with a patterned layer, for example, a photo resist layer, which may exhibit line roughness. In one exemplary embodiment, the patterned layer may be an extreme ultraviolet (EUV) photo resist layer. In one method, selective deposition of additional material is provided on the EUV photo resist layer after patterning to provide improved roughness and lithographic structure height to allow for more process margin when transferring the pattern to a layer underlying the photo resist. The additional material is deposited selectively thicker in areas above the photo resist than in areas where the photo resist is not present, such as exposed areas between the photo resist pattern. Pattern transfer to a layer underlying the photo resist may then occur (for example via an etch) while the patterned photo resist and additional material above the photo resist may collectively operate as an etch mask.

Abstract: A method for providing etch selectivity in substrate processing is disclosed. More particularly, a plasma treatment is provided to a plurality of exposed structures comprised of varying materials. The plasma treatment will preferentially enhance the etch selectivity between at least two of the exposed structures. In one embodiment, the plurality of exposed structures are utilized as part of a multi-patterning substrate process. In one embodiment, the exposed structures may comprise an organic planarization layer and a spin-on-metal layer. The plasma treatment may comprise a plasma formed using nitrogen and hydrogen gasses and the emission of vacuum ultra-violet (VUV) wavelength radiation from such a plasma.

Abstract: Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

Abstract: A self-aligned multiple patterning (SAMP) process is disclosed for formation of structures on substrates. The process provides improved local critical dimension uniformity by using a first (lower) multicolor array pattern and second (upper) multicolor array pattern. The dimensions of finally formed structures are defined by the overlap of a first spacer that is formed as part of the first multicolor array pattern and a second spacer that is formed as part of the second multicolor array pattern. The spacer widths which control the critical dimension of the formed structure may be highly uniform due to the nature of spacer formation and the use of an atomic layer deposition process for forming the spacer layers of the both first (lower) multicolor array pattern and second (upper) multicolor array pattern. In one embodiment, the structure formed by a memory hole pattern for a dynamic random access memory (DRAM).

Abstract: Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.

Abstract: Embodiments are disclosed that improve etch uniformity during multi-patterning processes for the manufacture of microelectronic workpieces by reshaping spacers using thermal decomposition materials as a protective layer. Because the thermal decomposition material can be removed through thermal treatment processes without requiring etch processes, spacers can be reshaped with no spacer profile change or damage while suppressing undesired gouging differences in underlying layers and related degradation in etch uniformity.

Abstract: A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.

Abstract: A self-aligned multiple patterning (SAMP) process is disclosed for formation of structures on substrates. The process provides improved local critical dimension uniformity by using a first (lower) multicolor array pattern and second (upper) multicolor array pattern. The dimensions of finally formed structures are defined by the overlap of a first spacer that is formed as part of the first multicolor array pattern and a second spacer that is formed as part of the second multicolor array pattern. The spacer widths which control the critical dimension of the formed structure may be highly uniform due to the nature of spacer formation and the use of an atomic layer deposition process for forming the spacer layers of the both first (lower) multicolor array pattern and second (upper) multicolor array pattern. In one embodiment, the structure formed by a memory hole pattern for a dynamic random access memory (DRAM).

Abstract: A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

Abstract: A substrate is provided with a patterned layer, for example, a photo resist layer, which may exhibit line roughness. In one exemplary embodiment, the patterned layer may be an extreme ultraviolet (EUV) photo resist layer. In one method, selective deposition of additional material is provided on the EUV photo resist layer after patterning to provide improved roughness and lithographic structure height to allow for more process margin when transferring the pattern to a layer underlying the photo resist. The additional material is deposited selectively thicker in areas above the photo resist than in areas where the photo resist is not present, such as exposed areas between the photo resist pattern. Pattern transfer to a layer underlying the photo resist may then occur (for example via an etch) while the patterned photo resist and additional material above the photo resist may collectively operate as an etch mask.

Abstract: A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.

Abstract: Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.

Abstract: Embodiments are disclosed that improve etch uniformity during multi-patterning processes for the manufacture of microelectronic workpieces by reshaping spacers using thermal decomposition materials as a protective layer. Because the thermal decomposition material can be removed through thermal treatment processes without requiring etch processes, spacers can be reshaped with no spacer profile change or damage while suppressing undesired gouging differences in underlying layers and related degradation in etch uniformity.

Abstract: A process is provided in which low-k layers are protected from damage caused by exposure to atmospheric conditions by providing protection through the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to coat exposed regions of the low-k layers so that the low-k layers are not exposed to atmospheric conditions. In an exemplary embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material. In another exemplary embodiment, trench and via openings in the low-k layer are plugged with the thermal decomposition material. The thermal decomposition materials may be removed by a heat based thermal anneal process step that does not damage the low-k layers.

Abstract: A process is provided in which low-k layers are protected from damage by the use of thermal decomposition materials. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. The thermal decomposition materials may be utilized to replace organic layers that typically require ashing processes to remove. By removing the need for certain ashing steps, the exposure of the low-k dielectric layer to ashing processes may be lessened. In another embodiment, the low-k layers may be protected by plugging openings in the low-k layer with the thermal decomposition material before a subsequent process step that may damage the low-k layer is performed. The thermal decomposition materials may be removed by a thermal anneal process step that does not damage the low-k layers.

Abstract: A method for providing etch selectivity in substrate processing is disclosed. More particularly, a plasma treatment is provided to a plurality of exposed structures comprised of varying materials. The plasma treatment will preferentially enhance the etch selectivity between at least two of the exposed structures. In one embodiment, the plurality of exposed structures are utilized as part of a multi-patterning substrate process. In one embodiment, the exposed structures may comprise an organic planarization layer and a spin-on-metal layer. The plasma treatment may comprise a plasma formed using nitrogen and hydrogen gasses and the emission of vacuum ultra-violet (VUV) wavelength radiation from such a plasma.

Abstract: A method of plasma etching includes an etching process that generates plasma from a process gas that includes fluorocarbon by using first high frequency power output by a first high frequency power source, and by the generated plasma, etches a low-k film with a metal-containing film as a mask. In the etching process, the first high frequency power is intermittently applied.

Abstract: A method of etching an insulation layer on an object to be processed in a process chamber in which an upper electrode and a lower electrode are placed facing each other, includes supplying a process gas that includes fluorocarbon gas and silicon tetrafluoride (SiF4) gas into the process chamber; applying high frequency power to at least one of the upper electrode and the lower electrode, to generate plasma; and etching the insulation layer by the generated plasma via a mask.