Patents by Inventor Toshihide Kawachi
Toshihide Kawachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9760017Abstract: According to one embodiment, wafer lithography equipment includes an exposure unit transferring a circuit pattern onto a wafer, a measurement unit measuring a dimension of the circuit pattern and a calculator. The calculator includes calculating a first difference. The first difference is the difference between a first dimension and a second dimension. The first dimension is obtained by substituting a first exposure amount and a first focus distance into an approximate response surface function. The second dimension is measured by the measurement unit. The calculator also includes calculating a second difference. The second difference is the sum total of the first difference for all of the circuit patterns. The calculator also includes calculating a second exposure amount and a second focus distance causing the difference between the approximate response surface function and the second difference to be a minimum. The calculator also includes calculating a correction exposure amount.Type: GrantFiled: July 20, 2015Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazufumi Shiozawa, Toshihide Kawachi, Masamichi Kishimoto, Nobuhiro Komine, Yoshimitsu Kato
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Publication number: 20160274470Abstract: According to one embodiment, wafer lithography equipment includes an exposure unit transferring a circuit pattern onto a wafer, a measurement unit measuring a dimension of the circuit pattern and a calculator. The calculator includes calculating a first difference. The first difference is the difference between a first dimension and a second dimension. The first dimension is obtained by substituting a first exposure amount and a first focus distance into an approximate response surface function. The second dimension is measured by the measurement unit. The calculator also includes calculating a second difference. The second difference is the sum total of the first difference for all of the circuit patterns. The calculator also includes calculating a second exposure amount and a second focus distance causing the difference between the approximate response surface function and the second difference to be a minimum. The calculator also includes calculating a correction exposure amount.Type: ApplicationFiled: July 20, 2015Publication date: September 22, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Kazufumi SHIOZAWA, Toshihide KAWACHI, Masamichi KISHIMOTO, Nobuhiro KOMINE, Yoshimitsu KATO
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Patent number: 8043772Abstract: In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.Type: GrantFiled: May 15, 2009Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventors: Toshiharu Miwa, Junko Konishi, Toshihide Kawachi, Shigenori Yamashita, Takeshi Tashiro, Hidekimi Fudo
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Patent number: 7879516Abstract: In the semiconductor integrated circuit device lithography process it is becoming more and more essential to control both exposure dose and focus value independently with a high accuracy. Using a wafer treated precedingly, a section profile of a photoresist is acquired by the technique of scatterometry, then both exposure dose and focus value are estimated independently with a high accuracy on the basis of the section profile thus acquired and using a conjectural expression obtained by the technique of multivariate analysis, and a focus setting in the exposure of a succeedingly treated wafer is corrected on the basis of the estimated exposure dose and focus value.Type: GrantFiled: April 11, 2008Date of Patent: February 1, 2011Assignee: Renesas Electronics CorporationInventors: Toshihide Kawachi, Hidekimi Fudo
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Publication number: 20090286174Abstract: In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at past time are measured, a resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of these measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of these estimated resist dimension and focus position, and then, an exposure dose is calculated as considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using these calculated exposure dose and focus offset value.Type: ApplicationFiled: May 15, 2009Publication date: November 19, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toshiharu MIWA, Junko KONISHI, Toshihide KAWACHI, Shigenori YAMASHITA, Takeshi TASHIRO, Hidekimi FUDO
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Publication number: 20080292977Abstract: In the semiconductor integrated circuit device lithography process it is becoming more and more essential to control both exposure dose and focus value independently with a high accuracy. Using a wafer treated precedingly, a section profile of a photoresist is acquired by the technique of scatterometry, then both exposure dose and focus value are estimated independently with a high accuracy on the basis of the section profile thus acquired and using a conjectural expression obtained by the technique of multivariate analysis, and a focus setting in the exposure of a succeedingly treated wafer is corrected on the basis of the estimated exposure dose and focus value.Type: ApplicationFiled: April 11, 2008Publication date: November 27, 2008Inventors: Toshihide KAWACHI, Hidekimi Fudo
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Patent number: 6617080Abstract: The present invention provides a photomask, a semiconductor device, and a method for exposing through the photomask. The photomask comprises a photomask substrate, and an on-mask circuit area including an on-mask circuit pattern and an on-mask test mark area including an on-mask test pattern, both formed on the surface of the substrate, wherein the photomask substrate further includes an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern. The present invention allows it to measure the actual displacement generated from an overlaying (i.e. alignment) process for the purpose of eliminating of an the overlay displacement which can take place in a photolithography process.Type: GrantFiled: May 2, 2000Date of Patent: September 9, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshihide Kawachi, Takuya Matsushita, Shigenori Yamashita, Yuki Miyamoto, Atsushi Ueno, Shinroku Maejima
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Patent number: 5868560Abstract: A reticle that allows deviation in rotation and magnification of an exposure region detected just using a wafer subjected to exposure and development without having to provide an underlying pattern, a pattern transferred using such a reticle, and a correction method are achieved. A first measurement pattern is provided on a dicing line pattern of the X axis direction. Also, a second measurement pattern is formed on a line of extension of the first measurement pattern in the Y axis direction. Similarly, a third measurement pattern is formed on the dicing line pattern in the Y axis direction. A fourth measurement pattern is provided corresponding to the third measurement pattern.Type: GrantFiled: September 30, 1997Date of Patent: February 9, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Naohisa Tamada, Toshihide Kawachi, Yuki Miyamoto