Patents by Inventor Toshihide TOBITSUKA

Toshihide TOBITSUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10096654
    Abstract: An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: October 9, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shin Kikuchi, Kazushi Komeda, Takuya Futase, Teruyuki Mine, Seje Takaki, Eiji Hayashi, Toshihide Tobitsuka
  • Publication number: 20170077184
    Abstract: An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.
    Type: Application
    Filed: September 11, 2015
    Publication date: March 16, 2017
    Inventors: Shin KIKUCHI, Kazushi KOMEDA, Takuya FUTASE, Teruyuki MINE, Seje TAKAKI, Eiji HAYASHI, Toshihide TOBITSUKA
  • Patent number: 9515023
    Abstract: A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. Optionally, a plurality of electrically conductive via connections can be formed, which have top surfaces within a same horizontal plane, have bottom surfaces contacting a respective electrically conductive layer located at different levels, and are isolated from one another by at least one trench isolation structure.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 6, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Toshihide Tobitsuka, Seje Takaki
  • Publication number: 20150179577
    Abstract: A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. Optionally, a plurality of electrically conductive via connections can be formed, which have top surfaces within a same horizontal plane, have bottom surfaces contacting a respective electrically conductive layer located at different levels, and are isolated from one another by at least one trench isolation structure.
    Type: Application
    Filed: March 10, 2015
    Publication date: June 25, 2015
    Inventors: Toshihide TOBITSUKA, Seje TAKAKI