Abstract: A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.

Abstract: A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer between the first and second latch circuits. The area of the first contact pad is larger than that of the second contact pad.

Abstract: A semiconductor circuit is installed on a printed circuit board having a power wiring pattern and a ground wiring pattern that do not intersect. The semiconductor circuit includes a first power supply terminal and a first ground terminal for a first side of the semiconductor circuit, and a second power supply terminal and a second ground terminal for a second side opposing to the first side. The direction from the first power supply terminal to the first ground terminal is the same as the direction from the second power supply terminal to the second ground terminal.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.

Abstract: A microcomputer according to the present invention includes a first non-volatile storage unit, a first input terminal configured to input first key data, a second storage unit configured to store second key data that is different from the first key data, a second input terminal configured to input an encrypted program, a decrypting unit configured to decrypt the encrypted program using the first and the second key data, and a central processing unit configured to control storing a decrypted program decrypted by the decrypting unit to the first storage unit.

Abstract: A semiconductor circuit is installed on a printed circuit board having a first wiring pattern and a second wiring pattern. The semiconductor circuit includes a first power supply terminal and a first ground terminal which are provided for a first side of the semiconductor circuit. The first power supply terminal is connected with the first wiring pattern. The first ground terminal is connected with the second wiring pattern. A second power supply terminal and a second ground terminal are provided for a second side opposing to the first side. The second power supply terminal is connected with the first wiring pattern and the second ground terminal is connected with the second wiring pattern. The first and second power and ground terminals are arranged such that the first wiring pattern and the second wiring pattern do not intersect in a region of the wiring substrate corresponding to the semiconductor circuit.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.

Abstract: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer between the first and second latch circuits. The area of the first contact pad is larger than that of the second contact pad.

Abstract: An improved layout of transistors near LCD drive terminals in a CMOS semiconductor device to reduce a chip size without damaging resistances against electrostatic destruction and latch-up. MOSFETs whose sources are connected to neither an electric source nor a ground are selectively arranged between two protective diffusion layers having different polarities, connected to a terminal.

Abstract: A semiconductor device includes a CMOSFET, including n-channel and p-channel MOSFETs. A terminal is connected to a node connecting the drains of the MOSFETs. A pull-up or pull-down resistor is connected between the terminal and a power source potential. The pull-up or pull-down resistor is composed of two serially-connected resistances. One of the two serially connected resistances is connected to the terminal and is formed of a resistance material that does not form a pn junction with a semiconductor substrate, and the other of the two resistances is formed of a diffusion layer of conduction type that forms a pn junction with the semiconductor substrate.

Abstract: An information processing device according to the present invention includes a logical circuit which outputs a signal for indicating that an error correction has been conducted on a data, when an error check and correction (ECC) circuit detects and corrects an error of data at the time of reading data from a memory cell array of an electrically erasable programmable ROM (EEPROM). In the information processing device of the present invention, while the EEPROM outputs the correct data by means of the ECC circuit, it can be known whether there exists an error even in a part of the cells in the EEPROM, so that it is possible to alter an address of a memory cell containing an erroneous bit in the EEPROM or to change the EEPROM itself before malfunction occurs in the information processing device having the EEPROM due to a breakdown of the memory cells in the EEPROM.

Abstract: A semiconductor integrated circuit having a complementary MOS structure, comprises an output buffer control portion of a complementary MOS inverter structure for inputting a logical output of an internal logic circuit, an output buffering MOS transistor of a first conductive type for receiving output of the output buffer control portion as a gate input and externally outputting a logical output, and level shifting means for causing level shift of a source potential of a second conductive type MOS transistor to be lower than a power source potential in a magnitude corresponding to a threshold value of the second conductive type MOS transistor.

Abstract: A microcomputer having an electrically erasable and programmable nonvolatile memory into which data is written without prolonging the data write processing time, even when a data read request is issued during the data write processing operation. The microcomputer includes a data erasing/writing/reading control circuit which coordinates the writing and reading of data to and from memory. The control circuit includes a timer for counting a predetermined number of counts during the data write process corresponding to the time period required to positively write data into the memory. If a data read request occurs during the data write process, the counting of the timer is suspended while the data is read out from the memory. After the data read process is completed, the data write process is resumed, and the timer continues counting toward the predetermined count from the count at which it was suspended.

Abstract: An EEPROM device comprises a memory cell array having a plurality of non-volatile memory cells respectively disposed at locations defined by word lines and bit lines and memorizing pieces of data information in a rewriteable manner, respectively, a row address decoder circuit responsive to an address signal indicative of a row address for selectively activating one of the word lines, a column address decoder circuit responsive to an address signal indicative of a column address for selecting one of the bit lines, and a data control unit selectively carrying out erasing, write-in and read-out operations on one of the non-volatile memory cells, in which the row address decoder circuit is further operative to concurrently activate every second word line in the presence of the row address signal indicative of a first state and to concurrently activate the other word lines in the presence of the row address signal indicative of a second state in a testing mode of operation, and in which the data control unit carri

Abstract: A single data signal is transmitted by two transmitters to two radio zones having an overlapping zone therebetween. The data signal is frequency or phase modulated and is mixed in the transmitters with RF carrier waves of equal frequency. The data signal to one of the transmitters is delayed between 5.degree. and 50.degree. with respect to the original data signal to provide a phase difference between the transmitted signals.