Patents by Inventor Toshihide Uematsu

Toshihide Uematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8883566
    Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: November 11, 2014
    Assignees: Rohm Co., Ltd., Renesas Electronics Corporation
    Inventors: Tadahiro Morifuji, Haruo Shimamoto, Chuichi Miyazaki, Toshihide Uematsu, Yoshiyuki Abe
  • Publication number: 20140220740
    Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicants: ROHM CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Tadahiro MORIFUJI, Haruo SHIMAMOTO, Chuichi MIYAZAKI, Toshihide UEMATSU, Yoshiyuki ABE
  • Patent number: 8729698
    Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: May 20, 2014
    Assignees: Rohm Co., Ltd., Renesas Electronics Corporation
    Inventors: Tadahiro Morifuji, Haruo Shimamoto, Chuichi Miyazaki, Toshihide Uematsu, Yoshiyuki Abe
  • Patent number: 8546244
    Abstract: A method includes the steps of: (a) fixing a front surface of a wafer (semiconductor wafer) having the front surface, a plurality of chip regions formed on the front surface, a dicing region formed between the chip regions, and a rear surface opposite to the front surface to the supporting member; (b) in a state of having the wafer fixed to the supporting member, grinding the rear surface of the wafer to expose the rear surface; (c) in a state of having the wafer fixed to the supporting member, dividing the wafer into the chip regions; (d) etching side surfaces of the chip regions to remove crushed layers formed in the step (c) on the side surfaces and obtain a plurality of semiconductor chips. After the steps (e) and (d), the plurality of divided chip regions are peeled off from the supporting member to obtain a plurality of semiconductor chips.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Toshihide Uematsu, Haruo Shimamoto
  • Patent number: 8378459
    Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Toshihide Uematsu, Chuichi Miyazaki, Kazunari Suzuki, Yasuyuki Nakajima, Yoshiyuki Abe, Kenji Kohzu, Kosuke Kitaichi, Shinya Ogane
  • Publication number: 20120184068
    Abstract: A method includes the steps of: (a) fixing a front surface of a wafer (semiconductor wafer) having the front surface, a plurality of chip regions formed on the front surface, a dicing region formed between the chip regions, and a rear surface opposite to the front surface to the supporting member; (b) in a state of having the wafer fixed to the supporting member, grinding the rear surface of the wafer to expose the rear surface; (c) in a state of having the wafer fixed to the supporting member, dividing the wafer into the chip regions; (d) etching side surfaces of the chip regions to remove crushed layers formed in the step (c) on the side surfaces and obtain a plurality of semiconductor chips. After the steps (e) and (d), the plurality of divided chip regions are peeled off from the supporting member to obtain a plurality of semiconductor chips.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 19, 2012
    Inventors: Yoshiyuki ABE, Chuichi Miyazaki, Toshihide Uematsu, Haruo Shimamoto
  • Publication number: 20110074017
    Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 31, 2011
    Applicants: ROHM CO., LTD, RENESAS ELECTRONICS CORPORATION
    Inventors: Tadahiro MORIFUJI, Haruo Shimamoto, Chuichi Miyazaki, Toshihide Uematsu, Yoshiyuki Abe
  • Publication number: 20100308442
    Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 9, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro NAKA, Naotaka TANAKA, Toshihide UEMATSU, Chuichi MIYAZAKI, Kazunari SUZUKI, Yasuyuki NAKAJIMA, Yoshiyuki ABE, Kenji KOHZU, Kosuke KITAICHI, Shinya OGANE
  • Patent number: 7759224
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Publication number: 20080286948
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Application
    Filed: July 9, 2008
    Publication date: November 20, 2008
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Patent number: 7452787
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Publication number: 20050260829
    Abstract: The reliability of a thin semiconductor device is to be improved. A tape having a ring affixed to an outer periphery thereof is affixed to a main surface of a semiconductor wafer, and, in this state, a back surface of the semiconductor wafer is subjected to grinding and polishing to thin the wafer. Thereafter, the semiconductor wafer is conveyed to a dicing apparatus in a state in which the tape with the ring is affixed to the wafer main surface without peeling of the tape, and dicing is performed from the back surface side of the semiconductor wafer to divide the wafer into individual semiconductor chips. With this method, handling of the thin semiconductor wafer by rear surface processing can be facilitated. Besides, the manufacturing process can be simplified because the replacement of the tape is not needed at the time of shift from rear surface processing to the dicing process.
    Type: Application
    Filed: May 3, 2005
    Publication date: November 24, 2005
    Inventors: Toshihide Uematsu, Chuichi Miyazaki, Yoshiyuki Abe, Minoru Kimura
  • Publication number: 20050142815
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 30, 2005
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Patent number: 5015425
    Abstract: A manufacturing apparatus has a clean air supply means provided integrally with a part thereof for supplying clean air toward at least an area in which a workpiece exists, and an air discharge means disposed so as to face the clean air supply means across the workpiece and adapted to discharge the air to the outside of the apparatus. It is therefore possible for clean air to be constantly supplied to the workpiece area under positive pressure. Thus, there is no risk of dust generated not only inside but also outside the apparatus being moved to the vicinity of the workpiece. Accordingly, it is possible to prevent adhesion of dust to the surface of the workpiece by the apparatus alone and also possible to install the apparatus as desired.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: May 14, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Mimata, Toshihide Uematsu, Katsuhiro Tabata
  • Patent number: 4890780
    Abstract: A manufacturing apparatus has a clean air supply means provided integrally with a part thereof for supplying clean air toward at least an area in which a workpiece exists, and an air discharge means disposed so as to face the clean air supply means across the workpiece and adapted to discharge the air to the outside of the apparatus. It is therefore possible for clean air to be constantly supplied to the workpiece area under positive pressure. Thus, there is no risk of dust generated not only inside but also outside the apparatus being moved to the vicinity of the workpiece. Accordingly, it is possible to prevent adhesion of dust to the surface of the workpiece by the apparatus alone and also possible to install the apparatus as desired.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: January 2, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Mimata, Toshihide Uematsu, Katsuhiro Tabata