Patents by Inventor Toshihiko Harano
Toshihiko Harano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6890783Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: GrantFiled: September 12, 2002Date of Patent: May 10, 2005Assignee: NEC LCD Technologies, LTD.Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
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Patent number: 6740596Abstract: The photolithography processes for connecting the first conductive film pattern, which is a lower layer such as a gate electrode of a TFT, to a second conductive film pattern, which is an upper layer such as a source/drain electrode of a TFT are reduced by utilizing laminated films and a resist pattern formed thereon having different film thicknesses. Laminated films constituting the source/drain electrode are formed by depositing films on an insulating substrate on which the first conductive film pattern is formed, and the resist pattern is formed on the top layer of the laminated films, and then utilizing the film thickness difference of the resist pattern and the film composition of the laminated films, the short circuited wiring between the gate electrode and the source/drain electrode for an Electro-Static-Discharge protection circuit of the active matrix substrate can be formed by less photolithography processes than that in the manufacturing of the conventional active matrix substrate.Type: GrantFiled: July 11, 2001Date of Patent: May 25, 2004Assignee: NEC LCD Technologies, Ltd.Inventors: Takasuke Hayase, Hiroaki Tanaka, Shusaku Kido, Toshihiko Harano
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Patent number: 6632696Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: GrantFiled: December 20, 2000Date of Patent: October 14, 2003Assignee: NEC CorporationInventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
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Publication number: 20030013221Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: ApplicationFiled: September 12, 2002Publication date: January 16, 2003Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
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Publication number: 20020009890Abstract: The photolithography processes for connecting the first conductive film pattern, which is a lower layer such as a gate electrode of a TFT, to a second conductive film pattern, which is an upper layer such as a source/drain electrode of a TFT are reduced by utilizing laminated films and a resist pattern formed thereon having different film thicknesses. Laminated films constituting the source/drain electrode are formed by depositing films on an insulating substrate on which the first conductive film pattern is formed, and the resist pattern is formed on the top layer of the laminated films, and then utilizing the film thickness difference of the resist pattern and the film composition of the laminated films, the short circuited wiring between the gate electrode and the source/drain electrode for an Electro-Static-Discharge protection circuit of the active matrix substrate can be formed by less photolithography processes than that in the manufacturing of the conventional active matrix substrate.Type: ApplicationFiled: July 11, 2001Publication date: January 24, 2002Applicant: NEC CorporationInventors: Takasuke Hayase, Hiroaki Tanaka, Shusaku Kido, Toshihiko Harano
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Publication number: 20010010370Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: ApplicationFiled: December 20, 2000Publication date: August 2, 2001Applicant: NEC CorporationInventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi