Abstract: To provide a coating composition which forms a coating film having excellent fingerprint removability and having favorable abrasion resistance and transparency, and a molded product having a coating film made of a cured product of the composition. An active energy ray curable coating composition comprising an active energy ray curable polymerizable monomer (A), a water and oil repellency-imparting agent (B) and an active energy ray polymerization initiator (C), wherein the water and oil repellency-imparting agent (B) contains a water and oil repellency-imparting agent (B-T) having a moiety (b-1) exerting water and oil repellency, an active energy ray curable functional group (b-2) and a moiety (b-3) excellent in compatibility with the polymerizable monomer (A) and a molded product having a coating film made of a cured product of the composition.

Abstract: An optical disk of a system wherein a recording layer is to be irradiated with a laser beam through a thin film cover layer, wherein on the surface of the thin film cover layer, a hard coat layer is formed which is made of a cured product of an active energy ray curable composition comprising a polymerizable monomer (A), a colloidal silica (B), a lubricity-imparting agent (C) and an active energy ray polymerization initiator (D), as components. The lubricity-imparting agent (C) contains a lubricity-imparting agent (C-T) having, in one molecule, a moiety (c-1) exerting lubricity, a moiety (c-2) excellent in compatibility with the polymerizable monomer and an active energy ray curable functional group (c-3). In the optical disk of the present invention, the hard coat layer formed on the surface of the thin film cover layer is excellent in abrasion resistance, transparency and long-term surface lubricity.

Abstract: A method of manufacturing a semiconductor device is provided including: forming a groove in an insulation film; forming a lower electrode material film on the insulation film and in the groove; forming a ferroelectric material film on the lower electrode material film, on the insulation film and in the groove; forming an upper electrode material film on the ferroelectric material film, on the insulation film and in the groove; forming a capacitive element within the groove by removing the upper electrode material film and the ferroelectric material film from the insulation film and leaving the upper electrode material film and the ferroelectric material film within the groove by CMP-polishing the insulation film and the groove.

Abstract: The invention provides an improved semiconductor and an improved method for manufacturing the device. In a preferred embodiment, a gate electrode is formed on a semiconductor substrate through a gate dielectric layer. First and second impurity diffusion layers are formed in the semiconductor substrate on either side of the gate electrode, with the gate electrode interposed between the first and second impurity diffusion layers. Sidewall dielectric layers are formed on side surfaces of the gate electrode and configured so that the gate electrode has a width that increases gradually from a bottom of the gate electrode toward a top surface of the gate electrode. The first and second impurity diffusion layers are formed thick enough that the surfaces of the first and second impurity diffusion layers are higher than the interface between the semiconductor substrate and the gate dielectric layer.

Abstract: An objective of the present invention is to provide a method of fabricating a semiconductor device comprising a MIS field-effect transistor that makes it possible to prevent damage to edge portions of a gate oxide layer during ion implantation and also prevents the thickness of edge portions of a titanium silicide layer from becoming too great. Before n−-type regions 16 are formed, a silicon nitride layer 24 is formed to extend from corner portions 42 of a gate electrode 26 and over side surfaces of a gate oxide layer 20. Ion implantation is used to form the n−-type regions 16. The silicon nitride layer 24 has been positioned so as to shield the side surfaces of the gate oxide layer 20. This ensures that ions do not strike the side surfaces of the gate oxide layer 20 during the implantation. When a titanium silicide layer 28 is formed on the upper surface of the gate electrode 26, the silicide reaction of the silicon nitride layer 24 on the side surfaces of the gate electrode 26 is prevented.

Abstract: A semiconductor device has a wiring pattern formed by etching a conductive layer using a resist pattern as a mask. The semiconductor device includes a contact section and a wiring. The contact section is formed in an interlayer dielectric layer. The wiring has a connection region to be connected to the contact section. The connection region of the wiring has a generally square plan configuration. The wiring has an extension section extending in a non-wiring region in the connection region.

Abstract: The invention provides an improved semiconductor and an improved method for manufacturing the device. In a preferred embodiment, a gate electrode is formed on a semiconductor substrate through a gate dielectric layer. First and second impurity diffusion layers are formed in the semiconductor substrate on either side of the gate electrode, with the gate electrode interposed between the first and second impurity diffusion layers. Sidewall dielectric layers are formed on side surfaces of the gate electrode and configured so that the gate electrode has a width that increases gradually from a bottom of the gate electrode toward a top surface of the gate electrode. The first and second impurity diffusion layers are formed thick enough that the surfaces of the first and second impurity diffusion layers are higher than the interface between the semiconductor substrate and the gate dielectric layer.

Abstract: A transparent coated molded product comprising a transparent synthetic resin substrate and two or more transparent cured material layers provided on at least one part of the surface of the transparent synthetic resin substrate, wherein an inner layer in contact with the outermost layer of the two or more transparent cured material layers is an abrasion-resistant layer which is a cured material of an active energy ray-curable coating agent (A) containing a polyfunctional compounds (a) having at least 2 active energy ray-curable polymerizable functional groups and the outermost layer is a silica layer which is a cured material of a curable coating agent (B) of polysilazane or a curable coating agent (B) containing polysilazane.

Abstract: An objective of the present invention is to provide a method of fabricating a semiconductor device comprising a MIS field-effect transistor that makes it possible to prevent damage to edge portions of a gate oxide layer during ion implantation and also prevents the thickness of edge portions of a titanium silicide layer from becoming too great.

Abstract: The present invention provides a polysilazane composition which is excellent in an ultraviolet light absorbing property and is less colored at the time of curing, and a coated molded product having its cured material formed on a substrate surface.

Abstract: An objective of the present invention is to provide a method of fabricating a semiconductor device comprising a MIS field-effect transistor that makes it possible to prevent damage to edge portions of a gate oxide layer during ion implantation and also prevents the thickness of edge portions of a titanium silicide layer from becoming too great. Before n−-type regions 16 are formed, a silicon nitride layer 24 is formed to extend from corner portions 42 of a gate electrode 26 and over side surfaces of a gate oxide layer 20. Ion implantation is used to form the n−-type regions 16. The silicon nitride layer 24 has been positioned so as to shield the side surfaces of the gate oxide layer 20. This ensures that ions do not strike the side surfaces of the gate oxide layer 20 during the implantation. When a titanium silicide layer 28 is formed on the upper surface of the gate electrode 26, the silicide reaction of the silicon nitride layer 24 on the side surfaces of the gate electrode 26 is prevented.

Abstract: A semiconductor device has a contact section formed in an interlayer dielectric layer, a first wiring formed over the interlayer dielectric layer and disposed with a separation from the contact section shorter than a specified separation, and a second wiring having a connection region to be connected to the contact section. The connection region has a shape that covers at least the contact section and preferably has a square shape. The second wiring has extension sections extending in non-wiring regions in the connection region to be connected to the contact section. The extension sections are disposed on sides of the connection region other than sides thereof facing the first wiring.

Abstract: An objective of the present invention is to provide a method of fabricating a semiconductor device comprising a MIS field-effect transistor that makes it possible to prevent damage to edge portions of a gate oxide layer during ion implantation and also prevents the thickness of edge portions of a titanium silicide layer from becoming too great.

Abstract: An organic substrate provided with a light absorptive antireflection film, which contains an organic substrate, and a light absorbing film and a low refractive index film formed in this order on the substrate, to reduce reflection of incident light from the low refractive index film side, wherein the organic substrate has its surface plasma-treated, and a layer made essentially of at least one member selected from the group consisting of silicon, a silicon nitride, a silicon oxide and a silicon oxy-nitride, is formed between the plasma-treated substrate surface and the light absorbing film.

Abstract: A process for purifying a polyether, which comprises adding to a polyether (A) containing a first salt, water (B) and a compound (C) which is capable of reacting with an ion constituting the first salt to form a second salt which is essentially insoluble in the polyether (A), then removing water, followed by removing the second salt from the polyether (A).

Abstract: A process for purifying a polyether, which comprises adding to a polyether (A) containing a first salt, water (B) and a compound (C) which is capable of reacting with an ion constituting the first salt to form a second salt which is essentially insoluble in the polyether (A), then removing water, followed by removing the second salt from the polyether (A).

Abstract: A transparent, smooth and cross-linked polyurethane resin sheet prepared from a reaction-curable composition which comprises a high molecular weight polyol mixture (A) comprising a polyester polyol and/or a polycarbonate polyol, as its main components, and containing a diol and a trivalent or higher valent polyol, the average hydroxyl value of the mixture being from 40 to 120, and the equivalent ratio of (the trivalent or higher valent polyol)/(the diol) being from 0.1 to 0.8, a substantially bivalent chain extender (B) in an amount of from 1.9 to 6.0 equivalents per equivalent of the polyol mixture (A), and a substantially bivalent alicyclic or aliphatic polyisocyanate compound (C) in an amount of from 0.8 to 1.2 equivalents per equivalent of the sum of the polyol mixture (A) and the chain extender (B), as its main components.

Abstract: A semiconductor device comprising: a semiconductor substrate; a plurality of conductive layers in which impuries are doped in a silicon composing the substrate; a wiring layer formed on the substrate via a first insulating layer and made chiefly of the silicon; a second insulating layer covering a surface of the substrate at an area including the conductive layers and the wiring layer; contact holes communicating respectively with the conductive layers and the wiring layer, the contact holes being formed by removing a part of the second insulating layer; and a multilayer interconnection layer electrically connected with the conductive layers and/or the wiring layer via the contact holes. The multilayer interconnection layer including a conductive silicon layer made chiefly of a polycrystalline silicon and contacting the conductive layers and/or the wiring layer, a barrier metal layer contacting the conductive silicon layer, and a metal wiring layer contacting the barrier metal layer.

Abstract: A sidewall construction is utilized in the fabrication of semiconductor devices comprising planar type bipolar transistors wherein the width of the sidewall construction can be accuracy controlled which, in turn, controls accuracy the channel length of the base of the planar type bipolar transistors. This technique provides ways of preventing short circuiting between the formed transistor collector and emitter regions of the planar type bipolar transistors. The sidewall construction can also be employed in fabrication combination planar type bipolar/MIS type transistors resulting in higher density of these structures over the prior art laterally positioned structures.

Abstract: A sidewall construction is utilized in the method of manufacture of semiconductor devices comprising planar type bipolar transistors wherein the width of the sidewall construction can be accuracy controlled which, in turn, controls accuracy the channel length of the base of the planar type bipolar transistors. This technique provides ways of preventing short circuiting between the formed transistor collector and emitter regions of the planar type bipolar transistors. The sidewall construction can also be employed in fabrication combination planar type bipolar/MIS type transistors resulting in higher density of these structures over the prior art laterally positioned structures.