Patents by Inventor Toshihiko Hirobe

Toshihiko Hirobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6590629
    Abstract: A liquid crystal display including an active matrix substrate furnished with a matrix of TFTs, in which a plurality of TAB substrates each having a driver IC are connected to the active matrix substrate through an ACF, and the driver ICs are connected to source bus lines through the ACF. Also, adjacent driver ICs disposed on the mounting substrates are connected to each other through common connection lines formed on the active matrix substrate. Consequently, the size and weight of the mounting substrates used to provide the driver ICs and lines connected to the same can be reduced, thereby making it possible to provide a light and inexpensive liquid crystal display having a small frame edge portion.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: July 8, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihiko Hirobe, Tetsuya Tarui, Yoshitaka Hibino, Naofumi Kondo
  • Patent number: 6529251
    Abstract: A liquid crystal display device includes: a source electrode (gate electrode) having an Al or Al alloy layer; a pixel electrode provided above the source electrode (gate electrode); and interlayer insulator films interposed between the source electrode (gate electrode) and the pixel electrode by depositing a TFT protection film as an inorganic insulator film and an organic insulator film in this sequence when viewed from the source electrode, so as to cover the source electrode (gate electrode).
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: March 4, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshitaka Hibino, Tetsuya Tarui, Toshihiko Hirobe
  • Publication number: 20020126243
    Abstract: A liquid crystal display device includes: a source electrode (gate electrode) having an Al or Al alloy layer; a pixel electrode provided above the source electrode (gate electrode); and interlayer insulator films interposed between the source electrode (gate electrode) and the pixel electrode by depositing a TFT protection film as an inorganic insulator film and an organic insulator film in this sequence when viewed from the source electrode, so as to cover the source electrode (gate electrode).
    Type: Application
    Filed: February 17, 2000
    Publication date: September 12, 2002
    Inventors: Yoshitaka Hibino, Tetsuya Tarui, Toshihiko Hirobe
  • Patent number: 5343216
    Abstract: An active matrix substrate comprising picture element electrodes disposed in a matrix on a substrate, each of which is composed of divided electrodes, and an electrically conductive film on which two of said divided electrodes adjacent to each other are superposed in a manner to sandwich an insulating film therebetween so as to form a connection. The connection is irradiated with laser beams from the outside of the display apparatus when one of the divided electrodes brings about a picture element defect, so that both the divided electrodes can be electrically connected to each other, thereby attaining a correction of the picture element defect. A display apparatus using the active matrix substrate is also provided.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: August 30, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mikio Katayama, Hiroaki Kato, Takayoshi Nagayasu, Akihiko Imaya, Hidenori Negoto, Yuzuru Kanemori, Toshihiko Hirobe
  • Patent number: 5187551
    Abstract: A thin film semiconductor device and a liquid crystal display apparatus are provided wherein the thin film semiconductor device having light irradiated thereon is cut off by a conductor layer, and the ight can be prevented from reaching the semiconductor layer. As a result, the generation of carriers due to optical excitation does not occur and the off current can be reduced. Because there is no area where electric field intensity in an opposed direction to the source electrode and the drain electrode is weaker than the electric field intensity of the channel region in the semiconductor layer, even after an operation for a prolonged duration under the irradiation of light, carriers generated by optical excitation are not accumulated in the semiconductor layer, and the probability of trapping for the carriers into a gate insulating film is quite low, and therefore variations in the characteristics of the thin film semiconductor device are negligibly small.
    Type: Grant
    Filed: April 10, 1991
    Date of Patent: February 16, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hajime Shoji, Noriko Watanabe, Hiroshi Hamada, Hiroaki Kato, Toshio Takemoto, Toshihiko Hirobe
  • Patent number: 5151807
    Abstract: An active matrix substrate comprising picture element electrodes disposed in a matrix on a substrate, each of which is composed of divided electrodes, and an electrically conductive film on which two of said divided electrodes adjacent to each other are superposed in a manner to sandwich an insulating film therebetween so as to form a connection. The connection is irradiated with laser beams from the outside of the display apparatus when one of the divided electrodes brings about a picture element defect, so that both the divided electrodes can be electrically connected to each other, thereby attaining a correction of the picture element defect. A display apparatus using the active matrix substrate is also provided.
    Type: Grant
    Filed: January 30, 1990
    Date of Patent: September 29, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mikio Katayama, Hiroaki Kato, Takayoshi Nagayasu, Akihiko Imaya, Hidenori Negoto, Yuzuru Kanemori, Toshihiko Hirobe
  • Patent number: 5054887
    Abstract: An active matrix type liquid crystal display device includes a substrate on which a matrix picture element electrodes reside, TFTs which are disposed in the vicinity of each picture element electrodes, and capacitor electrodes are provided, each of which is opposed to one portion of each of the picture element electrodes. A dielectric lamination structure consisting of three insulating layers is formed between the picture element electrode and the capacitor electrode. The dielectric lamination structure includes an anodic oxidation film, a gate insulating layer and a protective insulating layer. The protective insulating layer further extending over the associated TFT.
    Type: Grant
    Filed: August 9, 1989
    Date of Patent: October 8, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroaki Kato, Toshihiko Hirobe, Yoshitaka Hibino
  • Patent number: 5051800
    Abstract: A thin film semiconductor device and a liquid crystal display apparatus is provided wherein the thin film semiconductor device having light irradiated thereon is cut off by a conductor layer, and the light can be prevented from reaching the semiconductor layer. As a result, the generation of carriers due to optical excitation does not occur and the off current of the device can be reduced. Because there is no area where the electric field intensity in an opposed direction to the source electrode and the drain electrode is weaker than the electric field intensity of the channel region in the semiconductor layer, even after operating the device for a prolonged duration under the irradiation of light, carriers generated by optical excitation are not accumulated in the semiconductor layer, and the probability of trapping the carriers into a gate insulating film is quite low, and therefore variations in the characteristics of the thin film semiconductor device are negligibly small.
    Type: Grant
    Filed: April 28, 1989
    Date of Patent: September 24, 1991
    Inventors: Hajime Shoji, Noriko Watanabe, Hiroshi Hamada, Hiroaki Kato, Toshio Takemoto, Toshihiko Hirobe
  • Patent number: 5036370
    Abstract: The production of a thin film transistor array device having a gate wiring on an insulated substrate. The gate wiring has an inner gate wiring having a first metal layer formed on the insulated substrate and a second metal layer whose etching speed is faster than that of the first metal layer, the first metal layer and the second metal layer being overlapped so as to constitute a dual structure, and an outer gate wiring covering the inner gate wiring.
    Type: Grant
    Filed: July 2, 1990
    Date of Patent: July 30, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Makoto Miyago, Hiroshi Oka, Akihiko Imaya, Hiroaki Kato, Takayoshi Nagayasu, Toshihiko Hirobe