Patents by Inventor Toshihiko Koju

Toshihiko Koju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11886848
    Abstract: A method, system, and computer-readable medium for binary translation cause a binary translator to combine raw binary code and compiler-produced metadata associated with a compiled program module. The binary translator is caused to further reconcile, using the compiler-produced metadata, original compiler-produced control flow information with how lower-level machine instructions comprise a control flow in the raw binary code, and original compiler-produced aliasing information with how lower-level machine instructions access the memory locations described by the aliasing information according to predetermined criteria. The binary translator further caused to prevent, copy propagation of values in temporary variables for decimal computations beyond offsets in the machine instructions where the temporary variables are killed.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Toshihiko Koju, Reid Copeland, David Kevin Siegwart, Jordan Ryan Zannier, Allan H. Kielstra
  • Publication number: 20230385041
    Abstract: A method, system, and computer-readable medium for binary translation cause a binary translator to combine raw binary code and compiler-produced metadata associated with a compiled program module. The binary translator is caused to further reconcile, using the compiler-produced metadata, original compiler-produced control flow information with how lower-level machine instructions comprise a control flow in the raw binary code, and original compiler-produced aliasing information with how lower-level machine instructions access the memory locations described by the aliasing information according to predetermined criteria. The binary translator further caused to prevent, copy propagation of values in temporary variables for decimal computations beyond offsets in the machine instructions where the temporary variables are killed.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Inventors: Toshihiko Koju, REID COPELAND, David Kevin Siegwart, Jordan Ryan Zannier, ALLAN H. KIELSTRA
  • Patent number: 11068246
    Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Reid T. Copeland, Toshihiko Koju
  • Patent number: 10776255
    Abstract: A method for automatic verification of optimization of high level constructs includes generating a first executable code by compiling a computer program that includes a high level construct. The compiling includes generating a first set of machine instructions for the high level construct and storing compile-time information for the high level construct. The method further includes optimizing the first executable code which includes converting the first executable code into an intermediate language representation. The optimization further includes generating a second executable code. For this, the method includes generating a second set of machine instructions for the high level construct from the intermediate language representation. If the behavior of the first set of machine instructions and the second set of machine instructions matches, the second set of machine instructions is included in the second executable code, otherwise the first set of machine instructions is included.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Iain Alexander Ireland, Reid Copeland, Allan H. Kielstra, David Siegwart, Toshihiko Koju
  • Patent number: 10303493
    Abstract: Methods and systems for cross-language program execution include setting a signature of a second programming language in a first program that is written in a first programming language. A second program that is written in the second programming language is called from the first program, such that the second program omits checks to verify a runtime environment for the second programming language based on the presence of the signature.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshihiko Koju, Ying Chau R. Mak, Toshio Suganuma
  • Patent number: 10241768
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Publication number: 20180143812
    Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.
    Type: Application
    Filed: January 17, 2018
    Publication date: May 24, 2018
    Inventors: REID T. COPELAND, TOSHIHIKO KOJU
  • Publication number: 20180129517
    Abstract: Methods and systems for cross-language program execution include setting a signature of a second programming language in a first program that is written in a first programming language. A second program that is written in the second programming language is called from the first program, such that the second program omits checks to verify a runtime environment for the second programming language based on the presence of the signature.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 10, 2018
    Inventors: Toshihiko Koju, Ying Chau R. Mak, Toshio Suganuma
  • Patent number: 9921814
    Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Reid T. Copeland, Toshihiko Koju
  • Patent number: 9858054
    Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshihiko Koju, Ali I Sheikh
  • Patent number: 9760357
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Publication number: 20170161041
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Application
    Filed: February 21, 2017
    Publication date: June 8, 2017
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Patent number: 9626169
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Publication number: 20170060589
    Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.
    Type: Application
    Filed: August 24, 2015
    Publication date: March 2, 2017
    Inventors: REID T. COPELAND, TOSHIHIKO KOJU
  • Patent number: 9569347
    Abstract: Various embodiments test an optimized binary module. In one embodiment, a region in a set of original binary code of an original binary module in which branch coverage is expected to be achieved is selected based on a set of profile information. The region is selected as a target region to be optimized. An optimized binary module is created, where the target region has been optimized in the optimized binary module. The optimized binary module is verified by synchronizing execution of the optimized binary module with execution of the original binary module at a checkpoint while executing both the optimized binary module and the original binary module. The optimized binary module is further verified by comparing an output from executing the optimized binary module to an output from executing the original binary module.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Toshihiko Koju, Takuya Nakaike
  • Patent number: 9563536
    Abstract: Without using a high-level programming language source code, a set of sync points is identified in an initial binary code. The initial binary code is executed at a first system. A value of the user data is captured from a user space of a memory as a baseline of the user data. A set of comparative sync points is identified in a second binary code. During an execution of the second binary code, a second value of the user data from a second user space of a second memory is found to fail in matching the baseline of the user data. An instruction before the comparative sync point in the second binary code is identified as a location of a faulty operation due to the failing.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Cooper, Reid T. Copeland, Toshihiko Koju, Roger H. E. Pett, Trong Truong
  • Patent number: 9563547
    Abstract: Various embodiments test an optimized binary module. In one embodiment, a region in a set of original binary code of an original binary module in which branch coverage is expected to be achieved is selected based on a set of profile information. The region is selected as a target region to be optimized. An optimized binary module is created, where the target region has been optimized in the optimized binary module. The optimized binary module is verified by synchronizing execution of the optimized binary module with execution of the original binary module at a checkpoint while executing both the optimized binary module and the original binary module. The optimized binary module is further verified by comparing an output from executing the optimized binary module to an output from executing the original binary module.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: February 7, 2017
    Inventors: Toshihiko Koju, Takuya Nakaike
  • Patent number: 9430205
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Publication number: 20160179492
    Abstract: An apparatus for controlling an execution of a binary code by multiple threads includes a detection unit configured to detect an occurrence of modification of a first part that is a part of a first binary code by a self-modifying code; a specifying unit configured to specify a second part that is a part corresponding to the first part in a second binary code acquired by converting the first binary code, in response to detection of the occurrence of modification of the first part by the self-modifying code; and a correction unit configured to correct the second part such that a specific thread that executes the second part of the second binary code among the multiple threads causes an exception.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Inventors: Motohiro Kawahito, Toshihiko Koju, Xin Tong
  • Publication number: 20160154635
    Abstract: A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and/or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and/or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Inventors: TOSHIHIKO KOJU, ALI I SHEIKH