Patents by Inventor Toshihiko Mano
Toshihiko Mano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6316790Abstract: Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly well suited for use in an active matrix substrate for a liquid crystal display panel. The liquid crystal display panels include an additional insulating layer formed between crossing orthogonal source lines and gate lines to provide a higher breakdown voltage between the source lines and gate lines than at the gate insulating layer of the thin film transistors.Type: GrantFiled: May 20, 1997Date of Patent: November 13, 2001Assignee: Seiko Epson CorporationInventors: Toshimoto Kodaira, Hiroyuki Oshima, Toshihiko Mano
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Patent number: 6294796Abstract: Thin film transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of between about 100 Å and 2500 Å which are thinner than at least a portion of the source and drain regions and active matrix assemblies including thin film transistors for improved electro-optical displays are provided.Type: GrantFiled: October 11, 1994Date of Patent: September 25, 2001Assignee: Seiko Epson CorporationInventors: Toshihiko Mano, Toshimoto Kodaira, Hiroyuki Oshima
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Patent number: 6242777Abstract: Thin film transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of between about 100 Å and 2500 Å which are thinner than at least a portion of the source and drain regions and active matrix assemblies including thin film transistors for improved electro-optical displays are provided.Type: GrantFiled: March 13, 1995Date of Patent: June 5, 2001Assignee: Seiko Epson CorporationInventors: Toshihiko Mano, Toshimoto Kodaira, Hiroyuki Oshima
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Patent number: 6037608Abstract: Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly well suited for use in an active matrix substrate for a liquid crystal display panel. The liquid crystal display panels include an additional insulating layer formed between crossing orthogonal source lines and gate lines to provide a higher breakdown voltage between the source lines and gate lines than at the gate insulating layer of the thin film transistors.Type: GrantFiled: May 3, 1994Date of Patent: March 14, 2000Assignee: Seiko Epson CorporationInventors: Toshimoto Kodaira, Hiroyuki Oshima, Toshihiko Mano
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Patent number: 5736751Abstract: Thin film transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of between about 100 .ANG. and 2500 .ANG. which are thinner than at least a portion of the source and drain regions and active matrix assemblies including thin film transistors for improved electro-optical displays are provided.Type: GrantFiled: March 30, 1995Date of Patent: April 7, 1998Assignee: Seiko Epson CorporationInventors: Toshihiko Mano, Toshimoto Kodaira, Hiroyuki Oshima
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Patent number: 5698864Abstract: Thin film transistors including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of between about 100 .ANG. and 2500 .ANG. which are thinner than at least a portion of the source and drain regions and active matrix assemblies including thin film transistors for improved electro-optical displays are provided.Type: GrantFiled: May 26, 1995Date of Patent: December 16, 1997Assignee: Seiko Epson CorporationInventors: Toshihiko Mano, Toshimoto Kodaira, Hiroyuki Oshima
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Patent number: 5677547Abstract: Improved thin film transistors resistant to static electricity induced line faults are provided. The thin film transistors formed in accordance with the invention are particularly well suited for use in an active matrix substrate for a liquid crystal display panel. The liquid crystal display panels include an additional layer formed between crossing source lines and gate lines to provide a higher breakdown voltage between the source lines and gate lines than at the gate insulating layer of the thin film transistors or at a display capacitor.Type: GrantFiled: June 5, 1995Date of Patent: October 14, 1997Assignee: Seiko Epson CorporationInventors: Toshimoto Kodaira, Hiroyuki Oshima, Toshihiko Mano
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Patent number: 5650637Abstract: Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly well suited for use in an active matrix substrate for a liquid crystal display panel. The liquid crystal display panels include an additional insulating layer formed between crossing orthogonal source lines and gate lines to provide a higher breakdown voltage between the source lines and gate lines than at the gate insulating layer of the thin film transistors.Type: GrantFiled: March 20, 1995Date of Patent: July 22, 1997Assignee: Seiko Epson CorporationInventors: Toshimoto Kodaira, Hiroyuki Oshima, Toshihiko Mano
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Patent number: 5573959Abstract: Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly well suited for use in an active matrix substrate for a liquid crystal display panel. The liquid crystal display panels include an additional insulating layer formed between crossing orthogonal source lines and gate lines to provide a higher breakdown voltage between the source lines and gate lines than at the gate insulating layer of the thin film transistors.Type: GrantFiled: May 19, 1995Date of Patent: November 12, 1996Assignee: Seiko Epson CorporationInventors: Toshimoto Kodaira, Hiroyuki Oshima, Toshihiko Mano
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Patent number: 5554861Abstract: Thin file transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of between about 100 .ANG. and 2500 .ANG. which are thinner than at least a portion of the source and drain regions and active matrix assemblies including thin film transistors for improved electro-optical displays are provided.Type: GrantFiled: February 14, 1995Date of Patent: September 10, 1996Assignee: Seiko Epson CorporationInventors: Toshihiko Mano, Toshimoto Kodaira, Hiroyuki Oshima
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Patent number: 5552615Abstract: Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly well suited for use in an active matrix substrate for a liquid crystal display panel. The liquid crystal display panels include an additional insulating layer formed between crossing orthogonal source lines and gate lines to provide a higher breakdown voltage between the source lines and gate lines than at the gate insulating layer of the thin film transistors.Type: GrantFiled: March 23, 1995Date of Patent: September 3, 1996Assignee: Seiko Epson CorporationInventors: Toshimoto Kodaira, Hiroyuki Oshima, Toshihiko Mano
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Patent number: 5474942Abstract: Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly well suited for use in an active matrix substrate for a liquid crystal display panel. The liquid crystal display panels include an additional insulating layer formed between crossing orthogonal source lines and gate lines to provide a higher breakdown voltage between the source lines and gate lines than at the gate insulating layer of the thin film transistors.Type: GrantFiled: May 3, 1994Date of Patent: December 12, 1995Assignee: Seiko Epson CorporationInventors: Toshimoto Kodaira, Hiroyuki Oshima, Toshihiko Mano
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Patent number: 5365079Abstract: Improved thin film transistors resistant to photo-induced current and having improved electrical contact between electrodes and the source or drain regions are provided. The thin film transistors formed in accordance with the invention are particularly well suited for use in an active matrix substrate for a liquid crystal display panel. The liquid crystal display panels include an additional insulating layer formed between crossing orthogonal source lines and gate lines to provide a higher breakdown voltage between the source lines and gate lines than at the gate insulating layer of the thin film transistors.Type: GrantFiled: February 5, 1993Date of Patent: November 15, 1994Assignee: Seiko Epson CorporationInventors: Toshimoto Kodaira, Hiroyuki Oshima, Toshihiko Mano
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Patent number: 5124768Abstract: Thin film transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of less than 2500 .ANG. and active matrix assemblies including thin film transistors provide improved thin-type displays.Type: GrantFiled: May 31, 1988Date of Patent: June 23, 1992Assignee: Seiko Epson CorporationInventors: Toshihiko Mano, Toshimoto Kodaira, Hiroyuki Ohshima
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Patent number: 4623908Abstract: The thin film transistor comprises a plurality of individual thin film transistors on a common insulating substrate with the plurality of individual thin film transistors being connected together in series. The gate electrode of each individual transistor of the plurality of thin film transistors is connected to form one common gate electrode for the overall transistor. Leakage current in the OFF condition is substantially reduced. Identical performance is achieved from the transistor with interchangeability in designating source and drain terminals, when a symmetry is provided such that the i-th transistor in a series of N is physically identical to the (N-i+1)-th transistor in the overall transistor.Type: GrantFiled: March 31, 1983Date of Patent: November 18, 1986Assignee: Seiko Epson Kabushiki KaishaInventors: Hiroyuki Oshima, Toshimoto Kodaira, Toshihiko Mano