Patents by Inventor Toshihiro Hachiyanagi
Toshihiro Hachiyanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10833154Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.Type: GrantFiled: September 18, 2018Date of Patent: November 10, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gordon M. Grivna, Steven M. Etter, Hiroyuki Suzuki, Miki Ichiyanagi, Toshihiro Hachiyanagi
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Publication number: 20190035886Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.Type: ApplicationFiled: September 18, 2018Publication date: January 31, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gordon M. GRIVNA, Steven M. ETTER, Hiroyuki SUZUKI, Miki ICHIYANAGI, Toshihiro HACHIYANAGI
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Patent number: 10115790Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.Type: GrantFiled: August 30, 2016Date of Patent: October 30, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gordon M. Grivna, Steve M. Etter, Hiroyuki Suzuki, Miki Ichiyanagi, Toshihiro Hachiyanagi
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Publication number: 20170084687Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.Type: ApplicationFiled: August 30, 2016Publication date: March 23, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gordon M. GRIVNA, Steve M. ETTER, Hiroyuki SUZUKI, Miki ICHIYANAGI, Toshihiro HACHIYANAGI
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Patent number: 8735997Abstract: A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.Type: GrantFiled: September 17, 2007Date of Patent: May 27, 2014Assignee: Semiconductor Components Industries, LLCInventors: Toshihiro Hachiyanagi, Masafumi Uehara, Katsuyoshi Anzai
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Patent number: 7611957Abstract: The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer.Type: GrantFiled: January 30, 2007Date of Patent: November 3, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Eiji Nishibe, Toshihiro Hachiyanagi
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Publication number: 20080067617Abstract: A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.Type: ApplicationFiled: September 17, 2007Publication date: March 20, 2008Inventors: Toshihiro Hachiyanagi, Masafumi Uehara, Katsuyoshi Anzai
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Publication number: 20070178636Abstract: The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer.Type: ApplicationFiled: January 30, 2007Publication date: August 2, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Eiji Nishibe, Toshihiro Hachiyanagi
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Patent number: 7157779Abstract: An operational withstand voltage of a high voltage MOS transistor is enhanced and a variation in a saturation current Idsat is suppressed. A gate insulation film is formed on a P-type semiconductor substrate. A gate electrode is formed on the gate insulation film. A first low impurity concentration source layer and a first low impurity concentration drain layer are formed by tilt angle ion implantation of double charge phosphorus ions (31P++) using the gate electrode as a mask. Then a second low impurity concentration source layer and a second low impurity drain layer are formed by tilt angle ion implantation of single charge phosphorus ions (31P+).Type: GrantFiled: October 7, 2004Date of Patent: January 2, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Eiji Nishibe, Toshihiro Hachiyanagi
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Publication number: 20050116285Abstract: An operational withstand voltage of a high voltage MOS transistor is enhanced. An N?-type drain layer is formed in a surface of a P-type semiconductor substrate to overlap a gate electrode so that a surface of the N?-type drain layer below the gate electrode becomes depleted when a drain-source voltage Vds greater than a gate-source voltage Vgs is applied to the N?-type drain layer. Consequently, a channel current Ie of the high voltage MOS transistor flows through deep region of the N?-type drain layer under the surface depletion layer to avoid flowing through the surface region at an edge of the N?-type drain layer where an electric field converges. This results in reduced substrate current Isub and enhanced operational withstand voltage.Type: ApplicationFiled: October 6, 2004Publication date: June 2, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Eiji Nishibe, Toshihiro Hachiyanagi
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Publication number: 20050104138Abstract: An operational withstand voltage of a high voltage MOS transistor is enhanced and a variation in a saturation current Idsat is suppressed. A gate insulation film is formed on a P-type semiconductor substrate. A gate electrode is formed on the gate insulation film. A first low impurity concentration source layer and a first low impurity concentration drain layer are formed by tilt angle ion implantation of double charge phosphorus ions (31P++) using the gate electrode as a mask. Then a second low impurity concentration source layer and a second low impurity drain layer are formed by tilt angle ion implantation of single charge phosphorus ions (31P+).Type: ApplicationFiled: October 7, 2004Publication date: May 19, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Eiji Nishibe, Toshihiro Hachiyanagi