Abstract: In the chroma killer detection for detecting the abnormality of the burst signal, in addition to the circuits (1004, 1005, 1006) for detecting the states of the components of the burst signal, which circuits are for selecting the cos ? data of the burst signal, circuits (1050, 1051, 1052) for detecting the states of the R-Y components, which circuits are for selecting sin ? data are employed for chroma killer detection. Thereby, it is possible to enhance the detection precision of the abnormality states of the burst signal and the precision for discrimination of the broadcasting system.

Abstract: In the chroma killer detection for detecting the abnormality of the burst signal, in addition to the circuits (1004, 1005, 1006) for detecting the states of the components of the burst signal, which circuits are for selecting the cos ? data of the burst signal, circuits (1050, 1051, 1052) for detecting the states of the R-Y components, which circuits are for selecting sin ? data are employed for chroma killer detection. Thereby, it is possible to enhance the detection precision of the abnormality states of the burst signal and the precision for discrimination of the broadcasting system.

Abstract: An NTSC system chrominance signal demodulation apparatus is provided with a clock timing change circuit for burst-locking an input signal under the state where the phase is shifted by 90 degrees for every line, and phase axis rotation circuits for performing phase axis rotation, thereby to enable conversion of the phase axis of the burst signal. Therefore, demodulation of a PAL system chrominance signal can be carried out as well as demodulation of an NTSC system chrominance signal, and thereby demodulation of chrominance signals can be carried out using a common device regardless of the broadcast systems such as NTSC and PAL. Further, demodulation of chrominance signals can be carried out even under adverse conditions such as weak electric field or level compression of the burst signal.

Abstract: A color demodulation circuit that can complement an unstable state of an output from an ACC circuit and can obtain stable color-difference outputs, regardless of a burst signal in a chrominance carrier signal. Normally, a selector connects an output from a first multiplier that controls an amplitude of an output from a band-pass filter using an output from the ACC circuit, to a color-difference output demodulation circuit. However, during a period in which there are abrupt changes in the burst signal, for example during a period in which the output from the ACC circuit becomes unstable such as at switching between a state including a burst and a state not including a burst, the selector connects an output from a second multiplier that controls the amplitude of the output from the band-pass filter using an ACC output monitor signal, to the color-difference demodulation circuit.

Abstract: This invention provides a data signal extraction apparatus that accurately extracts data from a data signal that is serially transmitted even when phase shift or the like occurs. According to this apparatus, a phase shift amount calculation circuit 13 calculates a phase shift amount S13, then a correction amount calculation circuit 14 calculates a correction amount S14 on the basis of the phase shift amount S13, an extraction interval correction circuit 10 corrects an extraction interval value S9 on the basis of the correction amount, and an extraction pulse generation circuit 11 generates an extraction pulse S11 on the basis of a corrected extraction interval value S10, thereby extracting data from a binary signal S8 on the basis of the extraction pulse.

Abstract: A broadcast text data sampling apparatus comprises an A/D converter for sampling a broadcast text signal supplied from the outside, with a sampling clock of a predetermined frequency, to convert the text signal into digital data; a binarization circuit for converting the digital data into a binary signal; a sampling pulse generation circuit for detecting the cycle of clock run-in of the broadcast text signal from the binary signal, obtaining a text data sampling interval value on the basis of the clock run-in cycle, sequentially calculating the positions of data in the binary signal, which data are positioned at intervals close to the sampling interval value, starting from a predetermined sampling start position, and generating a sampling pulse that designates the calculated data positions as data sampling positions; and a sampling circuit for sampling the text data from the binary signal on the basis of the sampling pulse.

Abstract: An NTSC system chrominance signal demodulation apparatus is provided with a clock timing change circuit for burst-locking an input signal under the state where the phase is shifted by 90 degrees for every line, and phase axis rotation circuits for performing phase axis rotation, thereby to enable conversion of the phase axis of the burst signal. Therefore, demodulation of a PAL system chrominance signal can be carried out as well as demodulation of an NTSC system chrominance signal, and thereby demodulation of chrominance signals can be carried out using a common device regardless of the broadcast systems such as NTSC and PAL. Further, demodulation of chrominance signals can be carried out even under adverse conditions such as weak electric field or level compression of the burst signal.

Abstract: The microcomputer includes a CPU, a ROM, an OSD circuit, a wait signal generation circuit and a bus switch circuit. The ROM stores a program to be executed by the CPU and display data to be on-screen displayed on a display. The OSD circuit reads the display data stored in the ROM and outputs the read data to the display. The wait signal generation circuit generates a wait signal having a first level of a first time period and a second level of a second time period repeated alternately. The wait signal generation circuit determines the length of the first time period according to the amount of the display data to be read from the ROM to the OSD circuit. The bus switch circuit establishes a bus between the OSD circuit and the ROM when the wait signal is in the first level, and establishes a bus between the CPU and the ROM when the wait signal is in the second level.

Abstract: A color demodulation circuit that can complement an unstable state of an output from an ACC circuit and can obtain stable color-difference outputs, regardless of a burst signal in a chrominance carrier signal. Normally, a selector connects an output from a first multiplier that controls an amplitude of an output from a band-pass filter using an output from the ACC circuit, to a color-difference output demodulation circuit. However, during a period in which there are abrupt changes in the burst signal, for example during a period in which the output from the ACC circuit becomes unstable such as at switching between a state including a burst and a state not including a burst, the selector connects an output from a second multiplier that controls the amplitude of the output from the band-pass filter using an ACC output monitor signal, to the color-difference demodulation circuit.

Abstract: A clock generation apparatus generates a synchronous clock based on an input analog signal. The average of maximum and minimum values of a digital signal in a predetermined period is used as a threshold. Rise and fall times which are times when the threshold and an approximated line of two values of the digital signal crosses are detected. The time intervals between the adjacent rise and fall times are obtained during a predetermined period. The minimum value of the time intervals is used as the input rate. The synchronous clock is output on the basis of the input rate and the rise and fall times. The synchronous clock and a comparison signal which is obtained by comparing the threshold and the digital signal are supplied to a latch circuit, thereby outputting a synchronous signal.

Abstract: This invention provides a data signal extraction apparatus that accurately extracts data from a data signal that is serially transmitted even when phase shift or the like occurs. According to this apparatus, a phase shift amount calculation circuit 13 calculates a phase shift amount S13, then a correction amount calculation circuit 14 calculates a correction amount S14 on the basis of the phase shift amount S13, an extraction interval correction circuit 10 corrects an extraction interval value S9 on the basis of the correction amount, and an extraction pulse generation circuit 11 generates an extraction pulse S11 on the basis of a corrected extraction interval value S10, thereby extracting data from a binary signal S8 on the basis of the extraction pulse.

Abstract: The microcomputer includes a CPU, a ROM, an OSD circuit, a wait signal generation circuit and a bus switch circuit. The ROM stores a program to be executed by the CPU and display data to be on-screen displayed on a display. The OSD circuit reads the display data stored in the ROM and outputs the read data to the display. The wait signal generation circuit generates a wait signal having a first level of a first time period and a second level of a second time period repeated alternately. The wait signal generation circuit determines the length of the first time period according to the amount of the display data to be read from the ROM to the OSD circuit. The bus switch circuit establishes a bus between the OSD circuit and the ROM when the wait signal is in the first level, and establishes a bus between the CPU and the ROM when the wait signal is in the second level.

Abstract: A broadcast text data sampling apparatus comprises an A/D converter for sampling a broadcast text signal supplied from the outside, with a sampling clock of a predetermined frequency, to convert the text signal into digital data; a binarization circuit for converting the digital data into a binary signal; a sampling pulse generation circuit for detecting the cycle of clock run-in of the broadcast text signal from the binary signal, obtaining a text data sampling interval value on the basis of the clock run-in cycle, sequentially calculating the positions of data in the binary signal, which data are positioned at intervals close to the sampling interval value, starting from a predetermined sampling start position, and generating a sampling pulse that designates the calculated data positions as data sampling positions; and a sampling circuit for sampling the text data from the binary signal on the basis of the sampling pulse.