Abstract: A charge port device includes a charge port provided in a port accommodation recess and a lid for concealing the port accommodation recess. A latch is provided in the port accommodation recess on an opposite side to a lid hinge with respect to the charge port. A slit is formed between a surface of a vehicle body and an outer circumferential edge of the lid while the lid is closed. A lamp is provided at a position in the port accommodation recess between the latch and the slit on an opposite side to the lid hinge with respect to the charge port and the position is not visible from outside while the lid is closed. Formed is a light-guiding reflection path that guides a light emitted from the lamp toward the above-mentioned slit as an indirect light by reflecting the light while the lid is closed.

Abstract: An electronic component module includes a board, a plurality of external terminals provided on a first surface of the board, and a first semiconductor chip provided on a region on the first surface surrounded by the plurality of external terminals. The first semiconductor chip protrudes more along a normal to the first surface than ends of the external terminals do.

Abstract: An electronic component module includes a board, a plurality of external terminals provided on a first surface of the board, and a first semiconductor chip provided on a region on the first surface surrounded by the plurality of external terminals. The first semiconductor chip more protrudes along a normal to the first surface than ends of the external terminals do.

Abstract: When it is detected that a write address signal and a read address signal coincide with each other during in the judgment range state, an address value of the write address signal is held to halt writing into a memory, whereby a video signal is outputted without mixing old and new frames therein. Therefore, a buffer area in the memory can be minimized, and an address control circuit can be appropriately controlled even when the frame frequency difference exceed a buffer capacity, thereby a frame synchronizer circuit that can output normal pictures is provided.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: A picture signal processing circuit capable of processing picture signals of various broadcast systems including the SECAM system, the PAL system and the NTSC system, wherein an FM demodulation circuit for demodulating a SECAM signal is used also as a portion of a burst frequency discrimination circuit. An input picture signal is demodulated by the FM demodulation circuit to obtain a frequency component thereof, and then a burst signal portion thereof is extracted by a burst extracting circuit. The extracted demodulated signal is integrated by an integration circuit, and compared with a predetermined value by a comparator, based on which the burst frequency is determined. Therefore, it is possible to instantaneously determine the burst frequency, and the circuit scale is reduced by sharing the FM demodulation circuit.

Abstract: The vertical sync signal generator includes: a vertical sync signal separation circuit for separating a vertical sync signal of an input luminance signal and outputting the separated signal as a first vertical sync signal; an automatic frequency control circuit for generating a second vertical sync signal having a repeat frequency corresponding with an average repeat frequency of the first vertical sync signal and outputting the generated signal; a vertical sync signal phase detection circuit for detecting whether or not the first vertical sync signal has two different periods repeated alternately and outputting the detection result as a decision signal; and a selector for receiving the first and second vertical sync signals, selecting the first vertical sync signal when the decision signal indicates that the first vertical sync signal has two different periods repeated alternately and otherwise selecting the second vertical sync signal and outputting the selected signal.

Abstract: In the invention, the pipe lines around permselective membranes and the surfaces of permselective membranes are intermittently disinfected by adding an inexpensive acid such as sulfuric acid or the like to pre-treated crude water so as to make the water have a pH of 4 or lower. Accordingly, the invention provides a method of surely disinfecting the permselective membranes in membrane separation systems.

Abstract: A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

Abstract: In the invention, the pipe lines around permselective membranes and the surfaces of permselective membranes are intermittently disinfected by adding an inexpensive acid such as sulfuric acid or the like to pre-treated crude water so as to make the water have a pH of 4 or lower. Accordingly, the invention provides a method of surely disinfecting the permselective membranes in membrane separation systems.

Abstract: An analog-to-digital converter for converting an analog television signal to a signal in compliance with a digital encoding standard is provided.

Abstract: In the invention, the pipe lines around permselective membranes and the surfaces of permselective membranes are intermittently disinfected by adding an inexpensive acid such as sulfuric acid or the like to pre-treated crude water so as to make the water have a pH of 4 or lower. Accordingly, the invention provides a method of surely disinfecting the permselective membranes in membrane separation systems.

Abstract: A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst locked clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst locked clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

Abstract: In digitally recording an analog video signal on a storage medium, a data selector selects first luminance and first chrominance signals output from a Y/C separator. In response, a clock select switch selects a first clock signal with a first frequency. D/A converters sample the first luminance and first chrominance signals, output from the separator, at the first frequency, thereby converting them into analog signals to be output to a monitor. In reading out a digitally recorded video signal from the storage medium, the selector selects second luminance and second chrominance signals output from a digital codec and a chroma encoder, respectively. In response, the switch selects a second clock signal with a second frequency. The D/A converters sample the second luminance and second chrominance signals, output from the codec and the encoder, respectively, at the second frequency, thereby converting them into analog signals to be output to the monitor.

Abstract: A multi-standard television receiver in accordance with the present invention includes a plurality of video signal processing blocks having tristate functions at their output terminals, at least one memory block used in common for a plurality of video signal processing blocks and a video signal processing selection means for selecting one of the video signal processing blocks and independently controlling the output terminals of the video signal processing blocks using elements having a tristate function and can reduce power consumption by working only a selected video signal processing block and stopping the other video signal processing blocks. Further, using elements having a tristate function, possibility of element breakdown at selection and control of the elements can be removed.

Abstract: A digital audio signal demodulation circuit comprises a synchronous detection circuit (18) and a muting circuit (17) for muting the output from an interpolation circuit (16) using a synchronization lock signal generated from the synchronous detection circuit (18) when synchronization has been lost. The differential signal output from the interpolation circuit (16) is muted by the muting circuit (17) and thereafter integrated by an integration circuit (19). Thus, an audio signal with high sound quality can be demodulated without producing interruption noise even when synchronization has been lost or forcible muting is done.

Abstract: An audio signal demodulating circuit comprises a counter circuit (11) for detecting the number of samples for which interpolation is to be successively made by counting the output from an error correction circuit (2) and an AND circuit 10 for taking the logical product of the output from the counter circuit and the mute signal generated when synchronization has been lost. If interpolation is to be successively made for m (integer) or more, an audio differential signal is muted using a mute signal so as to remove the signal with greatly deteriorated audio quality. This can remove large audio distortion generated if interpolation is only successively made for error correction when errors successively occur for samples.

Abstract: The present invention provides an apparatus which receives and displays a high definition television signal and which is constructed so that noise and/or a deformed picture may not be displayed even when an input signal instead of a high definition television signal is applied or when transmission of such a high definition television signal is interrupted. In the apparatus, on the basis of whether or not a frame signal in an input high definition television signal can be detected, a first signal indicating synchronization lock or a second signal indicating synchronization unlock is generated so that, when the first signal is detected, the output of a signal processing circuit (110) is selected to display the high definition television signal, while when the second signal is detected, the output of a pattern generation circuit (114) is selected to prevent display of noise etc.

Abstract: In processing the transfer of digital voice signals, an interframe deinterleave switching circuit automatically switches the interleaving length without requiring any switching signal from the external unit. The circuit detects a voice synchronizing signal, produces a switching signal when the voice synchronizing signal is not detected, and inputs the switching signal to an interframe deinterleaving circuit (I) so that the interleaving length is automatically switched in synchronism therewith.

Abstract: An apparatus for receiving and selecting high-definition television signals and NTSC standard television signals includes a high-definition display screen device having an aspect ratio of 16 to 9. The NTSC standard television signals have an aspect ratio which is different than the 16 to 9 aspect ratio of the high-definition display screen device. A first signal converter is for converting the NTSC standard television signals into first quasi-high-definition television signals identifying a first displayed image corresponding in vertical length to a vertical length of the high-definition display screen device. A second signal converter is for converting the NTSC standard television signals into second quasi-high-definition television signals identifying a second displayed image corresponding in horizontal length to a horizontal length of the high-definition display screen device.