Patents by Inventor Toshihiro Nakamura

Toshihiro Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8826697
    Abstract: There is provided a method of manufacturing a plate member including preparing a base plate member having main faces, and performing etching by immersing at least part of the base plate member in an etching liquid while controlling a lowering speed of a liquid surface of the etching liquid on the main faces of the base plate member to a desired lowering speed.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: September 9, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventor: Toshihiro Nakamura
  • Patent number: 8791749
    Abstract: A power generation block configured to generate internal power by a charge pump circuit and a power supply control block configured to control the power generation block are provided. First and second power supply interconnects individually separated from an external power supply interconnect are connected to the power generation block and the power supply control block, respectively. At least any one of the power supply interconnects is provided with a filter section configured to remove noise propagating through the power supply interconnect.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: July 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshihiro Nakamura, Yuji Yamasaki, Masanobu Hirose, Masahisa Iida
  • Patent number: 8778719
    Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 15, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Toshihiro Nakamura, Nobuaki Orita, Hisashi Koaizawa, Kenkichi Suzuki, Hiroshi Kuraseko, Michio Kondo
  • Patent number: 8673396
    Abstract: A method of continuously forming a thin film includes the step of: moving a glass substrate with a thin strip shape having a constant db/2(d+b), where d is a thickness thereof and b is a width thereof in a cross section thereof, within a range from 0.015 to 0.15 through a film depositing region in which a reaction gas is supplied and a temperature is controlled to be high so that the glass substrate is rapidly heated; and moving continuously the glass substrate, immediately after the film depositing region, to pass through a cooling region in which a temperature is lower than that of the film depositing region, so that the glass substrate is rapidly cooled and the thin film formed of a component of the reaction gas is formed on the glass substrate.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: March 18, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Toshihiro Nakamura, Sadayuki Toda, Hisashi Koaizawa
  • Patent number: 8418503
    Abstract: A sheet glass that has a side surface with an average surface roughness equal to or less than 0.2 ?m is provided. Furthermore, a method of manufacturing a sheet glass is provided that includes processing a base-material glass sheet to obtain a sheet glass that has a side surface with an average surface roughness equal to or less than 0.2 ?m. Moreover, a method of manufacturing a sheet glass is provided that includes processing a base-material glass sheet so that an average surface roughness of a side surface becomes equal to or less than a predetermined value according to a section modulus of the sheet glass that is to be manufactured.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: April 16, 2013
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Toshihiro Nakamura, Sadayuki Toda, Hisashi Koaizawa
  • Publication number: 20130031246
    Abstract: A network monitoring control apparatus includes: a traffic information acquisition unit to acquire traffic information of a network component included in a network; a decision information switching unit to set decision information for the network component based on a comparison result between the traffic information and one of a congestion decision threshold and a congestion recovery decision threshold of the network component; and a management information acquisition unit to acquire management information of the network component based on the decision information.
    Type: Application
    Filed: May 21, 2012
    Publication date: January 31, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Nakamura, Gaku Todokoro
  • Publication number: 20120198889
    Abstract: A manufacturing method of a glass strip, the method including a heating and drawing process of heating and softening a glass plate preform, drawing the glass plate preform to have a desired thickness, and forming a glass strip, wherein at the heating and drawing process, the glass plate preform is drawn so that an internal pressure of a heating furnace is kept positive relative to an atmospheric pressure and so that gas flows introduced to both surfaces of the glass plate preform, respectively are equal to each other within the heating furnace.
    Type: Application
    Filed: April 20, 2012
    Publication date: August 9, 2012
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Toshihiro Nakamura, Tetsuya Kumada, Yasuhiro Naka
  • Publication number: 20120034728
    Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.
    Type: Application
    Filed: September 6, 2011
    Publication date: February 9, 2012
    Applicant: Furukawa Electric Co, Ltd.
    Inventors: Toshihiro NAKAMURA, Nobuaki ORITA, Hisashi KOAIZAWA, Kenkichi SUZUKI, Hiroshi KURASEKO, Michio KONDO
  • Patent number: 8039927
    Abstract: The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear substrate itself. Adopting semiconductor as the thin film 4 forms a linear semiconductor thin film. The linear semiconductor substrate 1 or 2 of the present invention is produced by utilizing a fiber-drawing technique which is a fabricating technique of optical fibers.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: October 18, 2011
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Toshihiro Nakamura, Nobuaki Orita, Hisashi Koaizawa, Kenkichi Suzuki, Hiroshi Kuraseko, Michio Kondo
  • Publication number: 20110100059
    Abstract: A sheet glass that has a side surface with an average surface roughness equal to or less than 0.2 ?m is provided. Furthermore, a method of manufacturing a sheet glass is provided that includes processing a base-material glass sheet to obtain a sheet glass that has a side surface with an average surface roughness equal to or less than 0.2 ?m. Moreover, a method of manufacturing a sheet glass is provided that includes processing a base-material glass sheet so that an average surface roughness of a side surface becomes equal to or less than a predetermined value according to a section modulus of the sheet glass that is to be manufactured.
    Type: Application
    Filed: January 10, 2011
    Publication date: May 5, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Toshihiro NAKAMURA, Sadayuki TODA, Hisashi KOAIZAWA
  • Publication number: 20110099459
    Abstract: A semiconductor memory device includes a memory array, an error correction code circuit, and a timing control signal generator configured to, based on a first timing control signal used to control a timing at which data to be input to the error correction code circuit is transferred to the error correction code circuit, generate a second timing control signal used to control a timing at which data output from the error correction code circuit is transferred to another circuit. The timing control signal generator includes a circuit which is the same as or corresponds to at least a portion of the error correction code circuit, and is configured to delay a timing of the first timing control signal by a period of time corresponding to a delay time of the error correction code circuit, and output the second timing control signal, depending on the delayed timing.
    Type: Application
    Filed: December 28, 2010
    Publication date: April 28, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Toshihiro NAKAMURA, Masahisa IIda
  • Patent number: 7883778
    Abstract: A sheet glass that has a side surface with an average surface roughness equal to or less than 0.2 ?m is provided. Furthermore, a method of manufacturing a sheet glass is provided that includes processing a base-material glass sheet to obtain a sheet glass that has a side surface with an average surface roughness equal to or less than 0.2 ?m. Moreover, a method of manufacturing a sheet glass is provided that includes processing a base-material glass sheet so that an average surface roughness of a side surface becomes equal to or less than a predetermined value according to a section modulus of the sheet glass that is to be manufactured.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: February 8, 2011
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Toshihiro Nakamura, Sadayuki Toda, Hisashi Koaizawa
  • Publication number: 20110014428
    Abstract: There is provided a method of manufacturing a plate member including preparing a base plate member having main faces, and performing etching by immersing at least part of the base plate member in an etching liquid while controlling a lowering speed of a liquid surface of the etching liquid on the main faces of the base plate member to a desired lowering speed.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventor: Toshihiro NAKAMURA
  • Patent number: 7668743
    Abstract: An apparatus for planning a demand-supply scheme of a supply chain so as to increase the corporate profit. A demand-supply scheme including order receipt, order placement, purchase and supply in the unit of a month of each step of a supply chain that includes various steps, such as product sales steps, product-producing steps, steps of producing parts for producing products, etc. is set so that the order placement to each producing step becomes within an order receivable range that is calculated from the equipment, the manpower, the number of times of operation, etc. of the producing step. Furthermore, a demand-supply scheme is planned and changed so as to maximize a profitability index that is calculated by using a cost regarding the production of a product that includes a material cost, a manpower cost, and an equipment cost, a stock management cost, a transportation cost, etc.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: February 23, 2010
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kuniya Kaneko, Hidetsugu Kojima, Hayaaki Fujiyoshi, Toshihiro Nakamura, Motohisa Kondo, Hirosumi Suzuki, Kentaro Otokubo
  • Publication number: 20100021727
    Abstract: A method of continuously forming a thin film includes the step of: moving a glass substrate with a thin strip shape having a constant db/2(d+b), where d is a thickness thereof and b is a width thereof in a cross section thereof, within a range from 0.015 to 0.15 through a film depositing region in which a reaction gas is supplied and a temperature is controlled to be high so that the glass substrate is rapidly heated; and moving continuously the glass substrate, immediately after the film depositing region, to pass through a cooling region in which a temperature is lower than that of the film depositing region, so that the glass substrate is rapidly cooled and the thin film formed of a component of the reaction gas is formed on the glass substrate.
    Type: Application
    Filed: September 11, 2008
    Publication date: January 28, 2010
    Inventors: Toshihiro Nakamura, Sadayuki Toda, Hisashi Koaizawa
  • Patent number: 7643366
    Abstract: A plurality of memory macros, to which first power is supplied, and a logic circuit block, to which second power is supplied, are provided. The memory macros are collectively disposed as a memory block on a semiconductor chip, and memory power wires for supplying the first power to the memory macros that form the memory block are provided over the memory block.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Toshihiro Nakamura, Masanobu Hirose
  • Patent number: D673201
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: December 25, 2012
    Assignee: Sony Corporation
    Inventors: Toshihiro Nakamura, Tomonari Murakami
  • Patent number: D681711
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: May 7, 2013
    Assignee: Sony Corporation
    Inventors: Yasuhiro Ishibashi, Toshihiro Nakamura
  • Patent number: D687477
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: August 6, 2013
    Assignee: Sony Corporation
    Inventors: Hiroshi Yasutomi, Toshihiro Nakamura
  • Patent number: D715262
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: October 14, 2014
    Assignee: Sony Corporation
    Inventor: Toshihiro Nakamura