Abstract: The multiplexer includes a plurality of transmission gates each formed by four-terminal double insulated gate N-type and P-type field effect transistors connected in parallel. One of gates of the N-type gate field effect transistor is connected to a first threshold voltage control node, and a first resistor is connected between the first threshold voltage control node and a first threshold voltage control voltage source. One of gates of the P-type gate field effect transistor is connected to a second threshold voltage control node, and a second resistor is connected between the second threshold voltage control node and a second threshold voltage control voltage source.

Abstract: A multiplexer using an FTMOST and capable of achieving both increase in transfer rate and reduction in leakage current and an integrated circuit using the multiplexer are provided. The multiplexer includes a plurality of pass transistors each formed by a four-terminal double insulated gate field effect transistor. A second gate of the field effect transistor is connected to a threshold voltage control node, and a resistor is connected between the threshold voltage control node and a threshold voltage control voltage source. Also, the multiplexer includes a plurality of transmission gates each formed by four-terminal double insulated gate N-type and P-type field effect transistors connected in parallel. One of gates of the N-type gate field effect transistor is connected to a first threshold voltage control node, and a first resistor is connected between the first threshold voltage control node and a first threshold voltage control voltage source.

Abstract: The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.

Abstract: The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.

Abstract: In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.

Abstract: Upstanding thin-film channel regions 5 having different heights are formed between source regions 7 and drain regions 8 of MOS transistors, respectively.

Abstract: It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

Abstract: A dual-gate field effect transistor includes a substrate 1, a source 7-1, a drain 7-2, a vertical channel 5 provided between the source and the drain as rising from the substrate, a pair of gate insulation films 6-1 and 6-2 sandwiching the channel from a direction orthogonal to a carrier-running direction in the channel and a pair of gate electrodes 3-1 and 3-2 facing the vertical channel 5, respectively, via the pair of gate insulation films 6-1 and 6-2, wherein the pair of insulation films have different thicknesses t1 and t2. It is also possible that the pair of gate insulation films 6-1 and 6-2 have different permittivities ?1 and ?2 and that the pair of gate electrodes have different work functions ?1 and ?2. Thus, it is possible to set the threshold voltage of the dual-gate field effect transistor to a desired value when fabricating it. Furthermore, it is possible to avoid the problem of an increase in subthreshold slope that occurs in the prior art.

Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.

Abstract: In an insulated double gate FET, the threshold voltage during the operation of a transient response thereof is enabled to be arbitrarily and accurately controlled by a method that includes applying a first input signal intended to perform an ordinary logic operation to one of the gate electrodes thereof and applying, in response to this signal, a second signal that has a signal-level temporal-change direction as the first input signal and has at least one of the low level and the high level thereof shifted by a predetermined magnitude or endowed with a predetermined time difference or has the time slower or faster signal level change of the signal to the other gate electrode.

Abstract: In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.

Abstract: Upstanding thin-film channel regions 5 having different heights are formed between source regions 7 and drain regions 8 of MOS transistors, respectively.

Abstract: It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

Abstract: It is an object of the present invention to provide a high-speed and low-power logical unit formed of a master slice integrated circuit, which offers advantages of reducing the cost and time required for designing masks, and in which a faster operation can be achieved while consuming low power by controlling the operation mode of each logical device forming the logical unit according to the operating state of the corresponding logical device. The high-speed and low-power logical unit comprises a plurality of logical devices including control-voltage input terminals for controlling operation modes, a voltage supply circuit for generating a plurality of different control voltages; and a wiring pattern for supplying a control voltage from the voltage supply circuit for controlling each of the logical devices to operate in an operation mode determined according to an operation of the corresponding transistor to the control-voltage input terminal of the corresponding logical device.

Abstract: In a double gate FET, the threshold voltage during the operation of a transient response thereof is enabled to be arbitrarily and accurately controlled by a method that includes applying a first input signal intended to perform an ordinary logic operation to one of the gate electrodes thereof and applying, in response to this signal, a second signal that has a signal-level temporal-change direction as the first input signal and has at least one of the low level and the high level thereof shifted by a predetermined magnitude or endowed with a predetermined time difference or has the time slower or faster signal level change of the signal to the other gate electrode.

Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.

Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.

Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.

Abstract: Disclosed herein is an improved field-effect transistor, having its effective base width determined by the impurity diffusion length or by a difference between impurity diffusion lengths for providing a reduced parasitic capacitance between gate and drain, and/or between gate or drain and other electrode. Disclosed also is a construction for effectively leading out an electrode from the base region and or source region, and methods adapted to manufacture the above-mentioned field-effect transistor.