Patents by Inventor Toshihiro Shinohara

Toshihiro Shinohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7520053
    Abstract: An object of the present invention is to manufacture a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments. A bump formation etching mask 7 is formed on the bump formation side 3a of a metal foil 3 having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit 1 and the height t2 of the bumps 2 to be formed on a wiring circuit 1, the bumps 2 are formed by half-etching the metal foil 3 from the bump formation etching mask 7 side down to a depth corresponding to a predetermined bump height t2, and a metal thin film layer 10 composed of a different metal from the metal foil 3 is formed on the bump formation side of the metal foil 3, thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: April 21, 2009
    Assignees: Sony Corporation, Sony Chemical & Information Device Corporation
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Patent number: 7098132
    Abstract: In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: August 29, 2006
    Assignees: Sony Chemicals Corp., Sony Corporation
    Inventors: Keiichi Naitoh, Toshihiro Shinohara, Masahiro Watanabe
  • Publication number: 20060070978
    Abstract: An object of the present invention is to manufacture a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments. A bump formation etching mask 7 is formed on the bump formation side 3a of a metal foil 3 having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit 1 and the height t2 of the bumps 2 to be formed on a wiring circuit 1, the bumps 2 are formed by half-etching the metal foil 3 from the bump formation etching mask 7 side down to a depth corresponding to a predetermined bump height t2, and a metal thin film layer 10 composed of a different metal from the metal foil 3 is formed on the bump formation side of the metal foil 3, thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments.
    Type: Application
    Filed: December 6, 2005
    Publication date: April 6, 2006
    Applicant: SONY CHEMICALS CORP.
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Patent number: 7020961
    Abstract: An object of the present invention is to manufacture a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments. A bump formation etching mask (7) is formed on the bump formation side (3a) of a metal foil (3) having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit (1) and the height t2 of the bumps (2) to be formed on a wiring circuit (1), the bumps (2) are formed by half-etching the metal foil (3) from the bump formation etching mask (7) side down to a depth corresponding to a predetermined bump height t2, and a metal thin film layer (10) composed of a different metal from the metal foil (3) is formed on the bump formation side of the metal foil (3), thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: April 4, 2006
    Assignee: Sony Corporation
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Patent number: 6977349
    Abstract: Wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other difficult operations are rendered unnecessary. By utilizing a technique whereby a bump-formation etching mask 7 is formed on a bump-forming surface 3a of a metal foil 3 which has a thickness that is the sum of the thickness t1 of the wiring circuit 1 and the height t2 of the bumps 2 which are to be formed on the wiring circuit 1 (t1+t2), and then the bumps 2 are formed by half-etching the metal foil 3 to a depth corresponding to the desired bump height t2 from the bump-formation etching mask 7 side, wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other complex processes are rendered unnecessary.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: December 20, 2005
    Assignees: Sony Corporation, Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Keiichi Naito, Toshihiro Shinohara
  • Publication number: 20050164492
    Abstract: In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.
    Type: Application
    Filed: March 23, 2005
    Publication date: July 28, 2005
    Applicant: Sony Chemicals Corp.
    Inventors: Keiichi Naitoh, Toshihiro Shinohara, Masahiro Watanabe
  • Patent number: 6912779
    Abstract: In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: July 5, 2005
    Assignee: Sony Chemicals Corp.
    Inventors: Keiichi Naitoh, Toshihiro Shinohara, Masahiro Watanabe
  • Patent number: 6840430
    Abstract: A board piece 2 of the present invention comprises a non-thermoplastic resin film 11, a thermoplastic resin film 10 formed on the non-thermoplastic resin film 11 and a metal wiring 8 formed on the surface of the thermoplastic resin film 10. Metal wiring 8 is partially exposed on board piece 2 to form a contact 12. A low-melting metal coating 13 is formed on contact 12 and two board pieces 2a, 2b are pressed against each other under heating with contacts 12a, 12b thereof being in contact with each other so that thermoplastic resin films 10a, 10b soften to adhere board pieces 2a, 2b to each other and low-melting metal coatings 13a, 13b melt and then solidify to connect contacts 12a, 12b to each other. The region of metal wiring 8 not used for connection is wiring 17 connecting contacts 12 to each other and a cover film 19 can be provided on the surface thereof. Contacts 12a, 12b can also be connected by applying ultrasonic wave.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: January 11, 2005
    Assignee: Sony Chemicals, Corp.
    Inventors: Hideyuki Kurita, Masanao Watanabe, Toshihiro Shinohara, Mitsuhiro Fukuda, Yukio Anzai
  • Publication number: 20040078970
    Abstract: In the present invention, a reference conductive layer and a first surface conductive layer are respectively provided on a surface and a back face of a first base film. The first base film includes a first via hole penetrating the first surface conductive layer. After a first electroless plating layer and a first conductive material are sequentially grown on a surface of the first base film, a first coating conductive layer composed of the first electroless plating layer, the first conductive material and the first surface conductive layer, is etched to have a reduced thickness. Then, the first coating conductive layer is patterned to form a first wiring layer. In this manner, a desired pattern width can be obtained even in the case where the first coating conductive layer is patterned by isotropic etching such as wet etching.
    Type: Application
    Filed: August 22, 2003
    Publication date: April 29, 2004
    Inventors: Keiichi Naitoh, Toshihiro Shinohara, Masahiro Watanabe
  • Publication number: 20030211234
    Abstract: A board piece 2 of the present invention comprises a non-thermoplastic resin film 11, a thermoplastic resin film 10 formed on the non-thermoplastic resin film 11 and a metal wiring 8 formed on the surface of the thermoplastic resin film 10. Metal wiring 8 is partially exposed on board piece 2 to form a contact 12. A low-melting metal coating 13 is formed on contact 12 and two board pieces 2a, 2b are pressed against each other under heating with contacts 12a, 12b thereof being in contact with each other so that thermoplastic resin films 10a, 10b soften to adhere board pieces 2a, 2b to each other and low-melting metal coatings 13a, 13b melt and then solidify to connect contacts 12a, 12b to each other. The region of metal wiring 8 not used for connection is wiring 17 connecting contacts 12 to each other and a cover film 19 can be provided on the surface thereof. Contacts 12a, 12b can also be connected by applying ultrasonic wave.
    Type: Application
    Filed: June 10, 2003
    Publication date: November 13, 2003
    Inventors: Hideyuki Kurita, Masanao Watanabe, Toshihiro Shinohara, Mitsuhiro Fukuda, Yukio Anzai
  • Publication number: 20030201242
    Abstract: Wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other difficult operations are rendered unnecessary. By utilizing a technique whereby a bump-formation etching mask 7 is formed on a bump-forming surface 3a of a metal foil 3 which has a thickness that is the sum of the thickness t1 of the wiring circuit 1 and the height t2 of the bumps 2 which are to be formed on the wiring circuit 1 (t1+t2), and then the bumps 2 are formed by half-etching the metal foil 3 to a depth corresponding to the desired bump height t2 from the bump-formation etching mask 7 side, wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other complex processes are rendered unnecessary.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 30, 2003
    Applicant: Sony Chemicals Corporation
    Inventors: Yutaka Kaneda, Keiichi Naito, Toshihiro Shinohara
  • Patent number: 6596947
    Abstract: A board piece 2 of the present invention comprises a non-thermoplastic resin film 11, a thermoplastic resin film 10 formed on the non-thermoplastic resin film 11 and a metal wiring 8 formed on the surface of the thermoplastic resin film 10. Metal wiring 8 is partially exposed on board piece 2 to form a contact 12. A low-melting metal coating 13 is formed on contact 12 and two board pieces 2a, 2b are pressed against each other under heating with contacts 12a, 12b thereof being in contact with each other so that thermoplastic resin films 10a, 10b soften to adhere board pieces 2a, 2b to each other and low-melting metal coatings 13a, 13b melt and then solidify to connect contacts 12a, 12b to each other. The region of metal wiring 8 not used for connection is wiring 17 connecting contacts 12 to each other and a cover film 19 can be provided on the surface thereof. Contacts 12a, 12b can also be connected by applying ultrasonic wave.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: July 22, 2003
    Assignee: Sony Chemicals Corp.
    Inventors: Hideyuki Kurita, Masanao Watanabe, Toshihiro Shinohara, Mitsuhiro Fukuda, Yukio Anzai
  • Patent number: 6562250
    Abstract: Wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other difficult operations are rendered unnecessary. By utilizing a technique whereby a bump-formation etching mask 7 is formed on a bump-forming surface 3a of a metal foil 3 which has a thickness that is the sum of the thickness t1 of the wiring circuit 1 and the height t2 of the bumps 2 which are to be formed on the wiring circuit 1 (t1+t2), and then the bumps 2 are formed by half-etching the metal foil 3 to a depth corresponding to the desired bump height t2 from the bump-formation etching mask 7 side, wiring circuit boards with bumps can be manufactured such that stable bump connections are possible and plating pre-treatments or other complex processes are rendered unnecessary.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: May 13, 2003
    Assignee: Sony Chemicals Corporation
    Inventors: Yutaka Kaneda, Keiichi Naito, Toshihiro Shinohara
  • Publication number: 20030034173
    Abstract: An object of the present invention is to manufacture a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments. A bump formation etching mask 7 is formed on the bump formation side 3a of a metal foil 3 having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit 1 and the height t2 of the bumps 2 to be formed on a wiring circuit 1, the bumps 2 are formed by half-etching the metal foil 3 from the bump formation etching mask 7 side down to a depth corresponding to a predetermined bump height t2, and a metal thin film layer 10 composed of a different metal from the metal foil 3 is formed on the bump formation side of the metal foil 3, thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments.
    Type: Application
    Filed: October 11, 2002
    Publication date: February 20, 2003
    Applicant: Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Patent number: 6518510
    Abstract: A bump formation etching mask is formed on the bump formation side of a metal foil having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit and the height t2 of the bumps to be formed on a wiring circuit. The bumps are formed by half-etching the metal foil from the bump formation etching mask side down to a depth corresponding to a predetermined bump height t2. A metal thin film layer formed of a different metal from the metal foil is formed on the bump formation side of the metal foil, thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations, such as plating pretreatments.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: February 11, 2003
    Assignee: Sony Chemicals Corp.
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Patent number: 6437251
    Abstract: This invention provides a specially-shaped, double-face flexible printed wiring board having a small pitch at a high production yield. Metal wirings 22 and 32 formed on a base film 21, 31 of two elemental pieces 20 and 30 of a flexible printed wiring board are arranged in such a manner as to face each other while sandwiching a bonding film 16 not containing conductive particles between them, and are heat-pressed to each other. The adhesive resin film 16 so softened is pushed aside from the metal wirings 22 and 32 and the low melting point metal coating films 23 and 33 formed on the surface of the metal wirings 22 and 32 come into direct contact with each other and are fused. In this instance, the softened adhesive resin film 16 is charged between the metal wirings 22 and 32. Therefore, the molten low melting point metal does not scatter. The base films 21 and 31 are bonded by the adhesive resin film 16.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: August 20, 2002
    Assignee: Sony Chemicals Corp.
    Inventors: Hideyuki Kurita, Masanao Watanabe, Toshihiro Shinohara, Yukio Anzai, Mitsuhiro Fukuda
  • Publication number: 20020005292
    Abstract: An object of the present invention is to manufacture a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments. A bump formation etching mask 7 is formed on the bump formation side 3a of a metal foil 3 having a thickness (t1+t2) equal to the sum of the thickness t1 of a wiring circuit 1 and the height t2 of the bumps 2 to be formed on a wiring circuit 1, the bumps 2 are formed by half-etching the metal foil 3 from the bump formation etching mask 7 side down to a depth corresponding to a predetermined bump height t2, and a metal thin film layer 10 composed of a different metal from the metal foil 3 is formed on the bump formation side of the metal foil 3, thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments.
    Type: Application
    Filed: July 2, 2001
    Publication date: January 17, 2002
    Applicant: SONY CHEMICALS CORP.
    Inventors: Yutaka Kaneda, Keiichi Naito, Soichiro Kishimoto, Toshihiro Shinohara
  • Patent number: 4390895
    Abstract: A color image pick-up apparatus using a single planar array of solid state light-sensitive elements with a color mosaic filter. The color mosaic filter is made up of three types of elements occurring in repeating patterns which are such that luminance-type elements occur at every other element portion along both of two orthogonal direction. The signal corresponding to luminance is separated from the output signal of the solid state light-sensitive elements and delayed for one horizontal scanning period. The high frequency component of the delayed signal is extracted. The extracted high frequency component signal is added to the signal corresponding to luminance which is succeedingly produced from the solid state light-sensitive elements.
    Type: Grant
    Filed: September 11, 1981
    Date of Patent: June 28, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Itsuzo Sato, Kazushige Ooi, Kikuo Saito, Yasuo Takemura, Toshihiro Shinohara