Abstract: A non-transitory computer-readable recording medium storing an acceleration test program for causing a computer to execute a process, the process includes selecting a cooperation application that operates in cooperation with a test target application that is a target application of an acceleration test by accelerating an operation of an application, determining an acceleration degree of an operation in an acceleration mode in which an operation of an application is accelerated in comparison to a normal mode, and disabling an acceleration of an operation of a non-cooperation application that does not cooperate with the test target application during an acceleration of operations of the test target application and the cooperation application based on the acceleration degree.

Abstract: A control apparatus that causes data in a first storage unit to be written in a second storage unit, with power supplied from a sub power supply, when supply of power from a main power supply is discontinued, the control apparatus includes a remaining feed duration obtaining unit that obtains remaining feed duration during which the sub power supply can supply the power; and a retry count setting unit that sets a maximum retry count for writing the data from the first storage unit to the second storage unit, based on the remaining feed duration obtained by the remaining feed duration obtaining unit, when an error occurs while the data is being written.

Abstract: An information processing device includes: a processor; a first storage device configured to hold data that is read and written by the processor; and a controller configured to control data transfer between the processor and the first storage device, wherein the controller: reads out first data from the first storage device through a path without a data protection function; generates error check information for checking an error of the first data; writes the error check information as first error check information in a storage area bypassing the path; writes the error check information as second error check information in the first storage device through the path; compares the first error check information and the second error check information to each other; and determines, when the first error check information and the second error check information do not match each other, that an error has occurred in the path.

Abstract: A control apparatus that causes data in a first storage unit to be written in a second storage unit, with power supplied from a sub power supply, when supply of power from a main power supply is discontinued, the control apparatus includes a remaining feed duration obtaining unit that obtains remaining feed duration during which the sub power supply can supply the power; and a retry count setting unit that sets a maximum retry count for writing the data from the first storage unit to the second storage unit, based on the remaining feed duration obtained by the remaining feed duration obtaining unit, when an error occurs while the data is being written.

Abstract: A relay device receives packets from an information processing apparatus or a relay device. The relay device updates a value of priority data indicating an accumulated wait time for arbitration contained in each of the received packets according to an elapsed time. The relay device selects a packet to be transmitted according to a result of comparison of the values of the pieces of the priority data contained in the received packets. The relay device transmits the selected packet to another relay device.

Abstract: A data transmission system includes a plurality of signal lines, a signal line determination unit, and a data transmission unit. The plurality of signal lines transmit data transmitted from a transmission-side device to a reception-side device. The signal line determination unit determines which signal line among the signal lines is used to transmit reception adjustment data to the reception-side device. The data transmission unit uses the signal line determined by the signal line determination unit to transmit the reception adjustment data to the reception-side device and uses another signal line to transmit transmission data to the reception-side device.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: A system includes a transmitting device configured to transmit a packet, and a receiving device connected through a switch device to the transmitting device, the receiving device being configured to receive the packet, wherein the switch device includes a first memory storing first expected value information indicative of an expected value of a fixed value region, the fixed value region being a region whose value is determined in advance in a transaction layer packet, and a switch control unit configured to compare a value of the fixed value region of the transaction layer packet received from the transmitting device with the expected value and make an error response to the transmitting device if the value of the fixed value region is different from the expected value.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.

Abstract: A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.