Patents by Inventor Toshiji Hamatani

Toshiji Hamatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7141821
    Abstract: The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: November 28, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Publication number: 20060261338
    Abstract: The invention primarily provides gate electrodes and gate wirings permitting large-sized screens for active matrix-type display devices, wherein, in order to achieve this object, the construction of the invention is a semiconductor device having, on the same substrate, a pixel TFT provided in a display region and a driver circuit TFT provided around the display region, wherein the gate electrodes of the pixel TFT and the driver circuit TFT are formed from a first conductive layer, the gate electrodes are in electrical contact through connectors with gate wirings formed from a second conductive layer, and the connectors are provided outside the channel-forming regions of the pixel TFT and the driver circuit TFT.
    Type: Application
    Filed: July 14, 2006
    Publication date: November 23, 2006
    Inventors: Shunpei Yamazaki, Jun Koyama, Toru Takayama, Toshiji Hamatani
  • Patent number: 7135741
    Abstract: A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103 disposed on a quartz substrate 101. A crystal silicon film 105 is obtained by this heat treatment. Then, a oxide film 106 is formed by wet oxidation. At this time, the nickel element is gettered to the oxide film 106 by an action of fluorite. Then, the oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: November 14, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Publication number: 20060249733
    Abstract: The invention primarily provides gate electrodes and gate wirings permitting large-sized screens for active matrix-type display devices, wherein, in order to achieve this object, the construction of the invention is a semiconductor device having, on the same substrate, a pixel TFT provided in a display region and a driver circuit TFT provided around the display region, wherein the gate electrodes of the pixel TFT and the driver circuit TFT are formed from a first conductive layer, the gate electrodes are in electrical contact through connectors with gate wirings formed from a second conductive layer, and the connectors are provided outside the channel-forming regions of the pixel TFT and the driver circuit TFT.
    Type: Application
    Filed: April 3, 2006
    Publication date: November 9, 2006
    Inventors: Shunpei Yamazaki, Jun Koyama, Toru Takayama, Toshiji Hamatani
  • Publication number: 20060249730
    Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.
    Type: Application
    Filed: July 10, 2006
    Publication date: November 9, 2006
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 7125334
    Abstract: A game machine for providing a game, the regularity of which cannot be easily recognized by the player, by making use of a chaotic random number produced by a random number generating means.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: October 24, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toshiji Hamatani, Norihiko Seo
  • Patent number: 7118996
    Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: October 10, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Koichiro Tanaka
  • Publication number: 20060208263
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Application
    Filed: May 12, 2006
    Publication date: September 21, 2006
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Patent number: 7078727
    Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: July 18, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 7057209
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: June 6, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Publication number: 20060105514
    Abstract: Two kinds of a thin film semiconductor unit are disposed over a substrate. A first thin film semiconductor unit includes a polycrystalline semiconductor thin film, and a second thin film semiconductor unit includes an amorphous semiconductor thin film.
    Type: Application
    Filed: December 19, 2005
    Publication date: May 18, 2006
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Takeshi Fukada
  • Publication number: 20060024925
    Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 2, 2006
    Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
  • Patent number: 6987036
    Abstract: The invention is directed to a countermeasure against a local amorphous region observed as an eddy pattern on a thermally crystallized crystalline silicon film. The local amorphous region is thought to result from a deficiently formed ultra-thin silicon oxide film by ozone water treatment, which causes a local phenomenon of repelling a catalyst element solution during spin coating. This inhibits a uniform addition of a catalyst element. A relationship between an ozone concentration of ozone water and a wait time between the ozone water treatment and the subsequent step of adding the catalyst element is deduced and used for planning the countermeasure against the local amorphous region.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: January 17, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki-ku Kaisha
    Inventors: Toshiji Hamatani, Misako Nakazawa, Naoki Makita
  • Publication number: 20060006348
    Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.
    Type: Application
    Filed: September 9, 2005
    Publication date: January 12, 2006
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Koichiro Tanaka
  • Patent number: 6977192
    Abstract: In manufacturing a thin film semiconductor device, a gate electrode forming step, a gate insulating film forming step, an amorphous semiconductor film forming step, a crystalline semiconductor film forming step, and an insulating film forming step are performed continuously without breaking vacuum.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: December 20, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Takeshi Fukada
  • Patent number: 6977394
    Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: December 20, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 6951802
    Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: October 4, 2005
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
  • Publication number: 20050205868
    Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.
    Type: Application
    Filed: March 23, 2005
    Publication date: September 22, 2005
    Applicant: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toshiji Hamatani
  • Publication number: 20050151132
    Abstract: A barrier layer that meets three requirements, “withstand well against etching and protect a semiconductor film from an etchant as an etching stopper”, “allow impurities to move in itself during heat treatment for gettering”, and “have excellent reproducibility”, is formed and used to getter impurities contained in a semiconductor film. The barrier layer is a silicon oxide film and the ratio of a sub-oxide contained in the barrier layer is 18% or higher.
    Type: Application
    Filed: February 3, 2005
    Publication date: July 14, 2005
    Applicants: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Misako Nakazawa, Mitsuhiro Ichijo, Toshiji Hamatani, Hideto Ohnuma, Naoki Makita
  • Patent number: 6889977
    Abstract: A game machine enabled to make various responses by adding the psychosomatic state and emotion of the player as one of conditions for determining the responding manner. The psychosomatic state of the player is grasped to change the responses in accordance with the psychological state of the player by making use of both a chaos attractor obtained by numerically processing the information sampled from the player and the index indicating the degree how the chaos attractor matches the defining condition of the chaos.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 10, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toshiji Hamatani