Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

Abstract: A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a first block that includes first and second sub-blocks. The memory controller instructs the non-volatile memory to execute a data erase process in units of sub-blocks on data stored in the non-volatile memory. In response to a first value corresponding to the first sub-block having reached a first threshold value, the memory controller reads first data from the first sub-block, executes an error correction process on the first data read from the first sub-block, and writes the first data on which the error correction process has been executed into the non-volatile memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

Abstract: A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.

Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m?1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.