Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11_1 and a second memory area 11_2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm_ are disposed in a boundary area 18 between the first and second memory areas 11_1 and 11_2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm— are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm— are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Abstract: A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.

Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Abstract: A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.

Abstract: A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.

Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Abstract: Provided is a semiconductor device including a step-down circuit group including multiple step-down circuits that step down an external power supply voltage to a predetermined voltage; multiple functional circuits that require a reset operation upon power-on; and a power-on reset circuit that outputs a reset command to the multiple functional circuits, when an internal power supply voltage supplied from the step-down circuit group exceeds a voltage level necessary for an initialization operation. The multiple step-down circuits of the step-down circuit group are classified into a startup operating step-down circuit group that performs a step-down operation from power-on to supply the internal power supply voltage, and a startup non-operating step-down circuit group that stops operation upon power-on to interrupt supply of the internal power supply voltage.

Abstract: A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.

Abstract: A power supply circuit comprises: a first voltage booster circuit that receives a first clock signal having a fixed frequency, and supplies a voltage to a prescribed circuit; and a second voltage booster circuit that receives a second clock signal having a frequency corresponding to an operating frequency of the prescribed circuit, and supplies a voltage to the prescribed circuit.

Abstract: A semiconductor device with technology for externally deciding if the stress test was performed or not. A semiconductor device includes a stress test circuit and a stress test decision circuit. The stress test circuit outputs control signals for executing the stress test to the stress test decision circuit and the object for testing. The stress test decision circuit then outputs the decision results if the stress test was performed, based on the control signals.

Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.

Abstract: Provided is a semiconductor device including a step-down circuit group including multiple step-down circuits that step down an external power supply voltage to a predetermined voltage; multiple functional circuits that require a reset operation upon power-on; and a power-on reset circuit that outputs a reset command to the multiple functional circuits, when an internal power supply voltage supplied from the step-down circuit group exceeds a voltage level necessary for an initialization operation. The multiple step-down circuits of the step-down circuit group are classified into a startup operating step-down circuit group that performs a step-down operation from power-on to supply the internal power supply voltage, and a startup non-operating step-down circuit group that stops operation upon power-on to interrupt supply of the internal power supply voltage.

Abstract: A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

Abstract: A semiconductor device with technology for externally deciding if the stress test was performed or not. A semiconductor device includes a stress test circuit and a stress test decision circuit. The stress test circuit outputs control signals for executing the stress test to the stress test decision circuit and the object for testing. The stress test decision circuit then outputs the decision results if the stress test was performed, based on the control signals.