Patents by Inventor Toshikazu Imaoka

Toshikazu Imaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8110895
    Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: February 7, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi
  • Patent number: 8110929
    Abstract: A semiconductor module includes: a substrate having a wiring layer; a first rectangular-shaped semiconductor device mounted on one surface of the substrate; a second rectangular-shaped semiconductor device mounted on the other surface of the substrate. The first semiconductor device is arranged such that each side thereof is not parallel to that of the second semiconductor device, and that the first semiconductor device is superimposed on the second semiconductor device, when seen from the direction perpendicular to the surface of the substrate.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: February 7, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Kenichi Kobayashi, Atsushi Nakano
  • Patent number: 8063846
    Abstract: A semiconductor module includes a multilayer board, a first circuit element mounted on the multilayer board, a second circuit element stacked on the first circuit element, an interposer board, provided between the first circuit element and the second circuit element, which includes an antenna conductor, a passive element, mounted on the multilayer board, which is connected to the antenna conductor, and a molded resin layer which seals the respective elements. The antenna conductor is structured by a spiral-shaped wiring pattern and the both ends of the antenna conductor are connected to the passive element via a bonding wire. The antenna conductor functions as a loop antenna with the passive element inserted.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 22, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Takeshi Otsuka, Tetsuro Sawai
  • Patent number: 7893539
    Abstract: A semiconductor apparatus includes: a wiring board; a first semiconductor device mounted on the wiring board; a second semiconductor device which is stacked on the first semiconductor device and a projection part projects from the outer edge of the first semiconductor device; and a sealing resin layer which seals each semiconductor device. And the second semiconductor device has thereon a first analog cell, and a second analog cell which reaches a higher temperature than the first analog cell, and the second analog cell is arranged so as to include the projection part of the second semiconductor device.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: February 22, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takeshi Otsuka, Toshikazu Imaoka
  • Patent number: 7875980
    Abstract: A technique for reducing the size of a semiconductor device is provided. A semiconductor device comprises a base, a semiconductor chip, a chip component, an insulating base, a wiring pattern, a via plug, an external lead-out electrode, a recess, and a resin. The insulating base has a multi-layer structure formed by laminating a plurality of insulator films. The semiconductor chip and the chip component are mounted on the base and embedded in the insulating base. A recess is formed on the surface of the semiconductor device and reaches down to any of wiring conductor layers. The semiconductor chip and the chip component are mounted on the recess.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: January 25, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Ryosuke Usui
  • Publication number: 20100315790
    Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 16, 2010
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi
  • Publication number: 20100252936
    Abstract: A semiconductor module includes: a substrate having a wiring layer; a first rectangular-shaped semiconductor device mounted on one surface of the substrate; a second rectangular-shaped semiconductor device mounted on the other surface of the substrate. The first semiconductor device is arranged such that each side thereof is not parallel to that of the second semiconductor device, and that the first semiconductor device is superimposed on the second semiconductor device, when seen from the direction perpendicular to the surface of the substrate.
    Type: Application
    Filed: May 27, 2008
    Publication date: October 7, 2010
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Kenichi Kobayashi, Atsushi Nakano
  • Patent number: 7750434
    Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: July 6, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi, Makoto Tsubonoya, Kazunari Kurokawa
  • Patent number: 7709941
    Abstract: A semiconductor pellet and chip components are provided on an insulating substrate, and are sealed with a molding resin that is molded by transfer molding. The chip components are positioned so as to surround the semiconductor pellet on all four sides. The lengthwise directions of the chip components surrounding the semiconductor pellet are aligned in a uniform direction. The insulating substrate is set within a die molding apparatus so that during resin injection, the lengthwise directions of the chip components are aligned substantially perpendicularly to the direction of flow of the injected resin.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: May 4, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Takeshi Yamaguchi, Ryosuke Usui, Hiroyuki Watanabe, Toshimichi Naruse, Atsushi Kato
  • Patent number: 7468645
    Abstract: A signal line circuit device is disposed on top of a mounting substrate. The signal line circuit device comprises a dielectric layer, a signal line formed on one surface of the dielectric layer, and a spacer (formed from a solder or a photo solder resist), which is formed between the mounting substrate and the dielectric layer, and generates a space separation between the signal line and the mounting substrate.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: December 23, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takeshi Yamaguchi, Toshikazu Imaoka
  • Patent number: 7453153
    Abstract: The ground noise is reduced which propagates between circuit elements in a circuit device having a multiple stack structure. A grounding bonding pad provided on the surface of a second circuit element is connected to a bonding wire provided on the surface of a conduction layer via a grounding wire such as gold. A bonding pad provided on the surface of the conductive layer is connected to a lead provided on a ground wire via a grounding wire such as gold. This structure creates a capacitance between the second circuit element and the conduction layer so as to prevent the propagation of noise circuit from element to the ground wiring.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: November 18, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai, Yasunori Inoue
  • Patent number: 7450397
    Abstract: A wiring board in which a line can be made narrower and/or a transmission loss can be reduced is developed. The wiring board includes a first conductor and a second conductor maintained at the same potential, a dielectric material layer provided between the first and second conductors, and a third conductor embedded in the dielectric material layer. In the wiring board, a thickness of the dielectric material layer in a first region located between the third conductor and the first conductor is larger than a thickness of the dielectric material layer in a second region located between the third conductor and the second conductor. Moreover, a cross-sectional shape of the third conductor is trapezoidal in which angles of respective ends of the third conductor on a side closer to the second conductor are obtuse.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: November 11, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai
  • Patent number: 7432580
    Abstract: A semiconductor apparatus comprises a substrate, a semiconductor chip fixedly secured on one side of the substrate, a spirally shaped coil formed on the other side of the substrate and electrically connected to the semiconductor chip, and a conductive pattern formed on a surface of the one side of the substrate facing to the semiconductor chip for stabilizing an inductance characteristic of the coil.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: October 7, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Akihiro Sato, Satoru Sekiguchi, Kiyokazu Kamado, Kazunari Kurokawa, Makoto Tsubonoya, Kiyoshi Mita, Yoichi Nabeta, Tetsuro Sawai, Toshikazu Imaoka
  • Publication number: 20080211110
    Abstract: A semiconductor apparatus includes: a wiring board; a first semiconductor device mounted on the wiring board; a second semiconductor device which is stacked on the first semiconductor device and a projection part projects from the outer edge of the first semiconductor device; and a sealing resin layer which seals each semiconductor device. And the second semiconductor device has thereon a first analog cell, and a second analog cell which reaches a higher temperature than the first analog cell, and the second analog cell is arranged so as to include the projection part of the second semiconductor device.
    Type: Application
    Filed: January 30, 2008
    Publication date: September 4, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Takeshi Otsuka, Toshikazu Imaoka
  • Publication number: 20080158091
    Abstract: A semiconductor module includes a multilayer board, a first circuit element mounted on the multilayer board, a second circuit element stacked on the first circuit element, an interposer board, provided between the first circuit element and the second circuit element, which includes an antenna conductor, a passive element, mounted on the multilayer board, which is connected to the antenna conductor, and a molded resin layer which seals the respective elements. The antenna conductor is structured by a spiral-shaped wiring pattern and the both ends of the antenna conductor are connected to the passive element via a bonding wire. The antenna conductor functions as a loop antenna with the passive element inserted.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 3, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Toshikazu Imaoka, Takeshi Otsuka, Tetsuro Sawai
  • Publication number: 20080078571
    Abstract: A device mounting board includes: a wiring layer; opposing signal wires formed on respective conductive layers, being arranged in parallel with each other; a pair of pad electrodes formed on the top of the wiring layer; a pair of pad electrodes formed on the bottom of the wiring layer; conductor parts which are formed through insulating layers and establish electrical connection between the top and bottom conductive layers; a circuit device mounted on the top side of the wiring layer; and a pair of signal electrodes formed on this circuit device, being connected to the pair of pad electrodes via conductive members. A line extending from one of the pad electrodes on the top to one of the pad electrodes on the bottom through one signal wire and a line extending from the other pad electrode on the top to the other pad electrode on the bottom through the other signal wire constitute a pair of differential transmission lines of equal lengths.
    Type: Application
    Filed: September 26, 2007
    Publication date: April 3, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Toshikazu Imaoka, Tetsuro Sawai
  • Publication number: 20070176303
    Abstract: A highly reliable circuit device is provided at low cost. The circuit device includes a semiconductor element electrically connected to a wiring layer (copper plate and plating film) and passive parts sealed by a molded resin layer. The wiring layer has a predetermined pattern formed by a conductive member. The molded resin layer has projections protruding from gaps in the adjacent wiring layer toward an underside of the wiring layer. Thereby, the drop of yield is prevented and the highly reliable circuit device is provided at low cost.
    Type: Application
    Filed: December 27, 2006
    Publication date: August 2, 2007
    Inventors: Makoto Murai, Ryosuke Usui, Tetsuro Sawai, Toshikazu Imaoka, Yasunori Inoue
  • Publication number: 20060238961
    Abstract: The ground noise is reduced which propagates between circuit elements in a circuit device having a multiple stack structure. A grounding bonding pad provided on the surface of a second circuit element is connected to a bonding wire provided on the surface of a conduction layer via a grounding wire such as gold. A bonding pad provided on the surface of the conductive layer is connected to a lead provided on a ground wire via a grounding wire such as gold. This structure creates a capacitance between the second circuit element and the conduction layer so as to prevent the propagation of noise circuit from element to the ground wiring.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 26, 2006
    Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai, Yasunori Inoue
  • Publication number: 20060216484
    Abstract: A wiring board in which a line can be made narrower and/or a transmission loss can be reduced is developed. The wiring board includes a first conductor and a second conductor maintained at the same potential, a dielectric material layer provided between the first and second conductors, and a third conductor embedded in the dielectric material layer. In the wiring board, a thickness of the dielectric material layer in a first region located between the third conductor and the first conductor is larger than a thickness of the dielectric material layer in a second region located between the third conductor and the second conductor. Moreover, a cross-sectional shape of the third conductor is trapezoidal in which angles of respective ends of the third conductor on a side closer to the second conductor are obtuse.
    Type: Application
    Filed: March 24, 2006
    Publication date: September 28, 2006
    Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai
  • Publication number: 20060170071
    Abstract: A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: abridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
    Type: Application
    Filed: January 20, 2006
    Publication date: August 3, 2006
    Inventors: Toshikazu Imaoka, Tetsuro Sawai, Atsushi Saita, Takeshi Yamaguchi, Makoto Tsubonoya, Kazunari Kurokawa