Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: Processing apparatus is disclosed, that comprises substrate container holding table that can hold substrate container that contains plurality of target substrates, first transferring chamber, disposed adjacent to the substrate container holding table, that maintains the interior at first pressure, first processing unit group, disposed around the first transferring chamber, that processes target substrate at the first pressure, first transferring mechanism, disposed in the first transferring chamber, that transfers target substrate, second transferring chamber, disposed adjacent to the first transferring chamber, that maintains the interior at second pressure, second processing unit group, disposed around the second transferring chamber, that processes target substrate at the second pressure, and second transferring mechanism, disposed in the second transferring chamber, wherein the first transferring mechanism and/or the second transferring mechanism has at least two transferring arms.

Abstract: Processing apparatus is disclosed, that comprises substrate container holding table that can hold substrate container that contains plurality of target substrates, first transferring chamber, disposed adjacent to the substrate container holding table, that maintains the interior at first pressure, first processing unit group, disposed around the first transferring chamber, that processes target substrate at the first pressure, first transferring mechanism, disposed in the first transferring chamber, that transfers target substrate, second transferring chamber, disposed adjacent to the first transferring chamber, that maintains the interior at second pressure, second processing unit group, disposed around the second transferring chamber, that processes target substrate at the second pressure, and second transferring mechanism, disposed in the second transferring chamber, wherein the first transferring mechanism and/or the second transferring mechanism has at least two transferring arms.

Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: Processing apparatus is disclosed, that comprises substrate container holding table that can hold substrate container that contains plurality of target substrates, first transferring chamber, disposed adjacent to the substrate container holding table, that maintains the interior at first pressure, first processing unit group, disposed around the first transferring chamber, that processes target substrate at the first pressure, first transferring mechanism, disposed in the first transferring chamber, that transfers target substrate, second transferring chamber, disposed adjacent to the first transferring chamber, that maintains the interior at second pressure, second processing unit group, disposed around the second transferring chamber, that processes target substrate at the second pressure, and second transferring mechanism, disposed in the second transferring chamber, wherein the first transferring mechanism and/or the second transferring mechanism has at least two transferring arms.

Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Abstract: A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.