Patents by Inventor Toshikazu Kuroda
Toshikazu Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7723794Abstract: A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.Type: GrantFiled: September 7, 2006Date of Patent: May 25, 2010Assignee: Oki Semiconductor Co., Ltd.Inventors: Toshikazu Kuroda, Hirokazu Hayashi, Yasuhiro Fukuda
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Patent number: 7671415Abstract: An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage.Type: GrantFiled: March 15, 2006Date of Patent: March 2, 2010Assignee: Oki Semiconductor Co., Ltd.Inventors: Toshikazu Kuroda, Hirokazu Hayashi, Yasuhiro Fukuda
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Patent number: 7498615Abstract: An electro-static discharge protection circuit includes a thyristor mode ensuring circuit and a thyristor rectifier circuit. The thyristor mode ensuring circuit includes a capacitive element connected between a higher potential line and a lower potential line, and ensures a constant and sufficient capacity independently of the number of input/output signal bits, even when the number of input/output signal bits is a theoretical minimum, i.e. 1, so that a surge current induced by electro-static discharge (ESD) applied to an output pad is injected into the first capacitive element to charge it. Thus, by means of the current caused by the surge current, the thyristor rectifier circuit is triggered into a thyristor mode, which allows the surge current to flow to the lower potential line through the thyristor rectifier circuit, protecting circuitry against the surge current.Type: GrantFiled: February 28, 2006Date of Patent: March 3, 2009Assignee: Oki Electric Industry Co., Ltd.Inventors: Toshikazu Kuroda, Hirokazu Hayashi, Yasuhiro Fukuda
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Patent number: 7238991Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.Type: GrantFiled: September 23, 2004Date of Patent: July 3, 2007Assignee: Oki Electric Industry Co., Ltd.Inventors: Toshikazu Kuroda, Katsuhito Sasaki
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Publication number: 20070052033Abstract: A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.Type: ApplicationFiled: September 7, 2006Publication date: March 8, 2007Inventors: Toshikazu Kuroda, Hirokazu Hayashi, Yasuhiro Fukuda
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Publication number: 20060220136Abstract: An electro-static discharge protection circuit comprises a thyristor mode ensuring circuit and a thyristor rectifier circuit. The thyristor mode ensuring circuit includes a capacitive element C1 connected between a higher potential line Vdd and a lower potential line Vss, and ensures a constant and sufficient capacity independently of the number of input/output signal bits, even when the number of input/output signal bits is the theoretical minimum, i.e. 1, so that a surge current induced by electro-static discharge (ESD) applied to an output pad Vout is injected into the first capacitive element C1 in order to charge it. Thus, by means of the current caused by the surge current, the thyristor rectifier circuit is triggered into a thyristor mode, which allows the surge current to flow to the lower potential line Vss through the thyristor rectifier circuit, resulting in a CMOS inverter of an internal circuitry being effectively protected against the surge current.Type: ApplicationFiled: February 28, 2006Publication date: October 5, 2006Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventors: Toshikazu KURODA, Hirokazau HAYASHI, Yasuhiro FUKUDA
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Publication number: 20060220137Abstract: An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage.Type: ApplicationFiled: March 15, 2006Publication date: October 5, 2006Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventors: Toshikazu KURODA, Hirokazu HAYASHI, Yasuhiro FUKUDA
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Publication number: 20050035416Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.Type: ApplicationFiled: September 23, 2004Publication date: February 17, 2005Inventors: Toshikazu Kuroda, Katsuhito Sasaki
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Patent number: 6798022Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.Type: GrantFiled: March 11, 2003Date of Patent: September 28, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Toshikazu Kuroda, Katsuhito Sasaki
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Publication number: 20040178454Abstract: A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.Type: ApplicationFiled: March 11, 2003Publication date: September 16, 2004Inventors: Toshikazu Kuroda, Katsuhito Sasaki
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Patent number: 5166082Abstract: This invention provides devices each of which has at least one bipolar transistor and at least one MOS transistor, both formed on a substrate. This invention also provides their fabrication process. Each device is constructed of epitaxial layers of a first and second conductivity types, surfaces of said epitaxial layers being partly exposed, at least one MOS transistor formed in the epitaxial layer of the first conductivity type, and at least one bipolar transistor formed in the epitaxial layer of the second conductivity type. Its fabrication process comprises the steps of forming the epitaxial layer of the second conductivity type on the semiconductor substrate, forming the epitaxial layer of the first conductivity type on a part of the epitaxial layer of the second conductivity type, forming the bipolar transistor in the epitaxial layer of the second conductivity type and then forming the MOS transistor in the epitaxial layer of the first conductivity type.Type: GrantFiled: June 10, 1991Date of Patent: November 24, 1992Assignee: Oki Electric Industry Co., Ltd.Inventors: Takaharu Nakamura, Toshikazu Kuroda, Tatsuya Kimura
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Patent number: 5128280Abstract: A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges. The process can be used to form wafer alignment marks having arbitrary patterns and can be adopted to improve the reliability of automatic alignment without the need to make new masks.Type: GrantFiled: July 19, 1991Date of Patent: July 7, 1992Assignee: Oki Electric Industry Co., Ltd.Inventors: Ryoichi Matsumoto, Toshikazu Kuroda, Takao Kato
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Patent number: 5106432Abstract: A wafer alignment mark consists of patterns, such as a chevron and two stripes, formed in the surface of a semiconductor wafer. Each pattern is defined by a pair of parallel grooves, separation between all pairs of grooves being the same. Each groove provides one sharp edge which can be reliably detected by an automatic alignment system.A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges.Type: GrantFiled: May 15, 1990Date of Patent: April 21, 1992Assignee: Oki Electric Industry Co., Ltd.Inventors: Ryoichi Matsumoto, Toshikazu Kuroda, Takao Kato