Abstract: By considering a Deep Nwell diffusing into a Pwell region, accuracy of a substrate parasitic-resistance extraction is improved. A well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate is divided into two or more meshes each including two or more resistor segments and a substrate noise is analyzed based thereon. In this regard, parallel components of resistors coupling the Pwell with the substrate are deleted in accordance with a state of the Deep Nwell diffusing into the Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value. By deleting the parallel components of the resistors coupling the Pwell with the substrate, the rise in the resistance value caused by the Deep Nwell can be reflected in the substrate parasitic-resistance extraction. Therefore, the accuracy of the substrate parasitic-resistance extraction can be improved.

Abstract: A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information.

Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.

Abstract: A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information.

Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.

Abstract: A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information.

Abstract: A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N1) is electrically connected to a terminal (P2) between the drains of PMOS and NMOS transistors (MP2, MN2). As a target capacitance forming part, a coupling capacitance (Cc) is formed between the node (N1) and a node (N2). The node (N2) is connected to a pad (58) through the terminal (P2) and an NMOS transistor (MN3), and a node (N3) is connected to a terminal (P3) between the drains of PMOS and NMOS transistors (MP1, MN1). A reference capacitance (Cref) is formed at the node (N3) as a dummy capacitance. Currents (Ir, It) supplied from a power source to the nodes (N3, N1) are measured with current meters (61, 62), respectively and a current (Im) induced from the node (N2) and flowing to a ground level is measured with a current meter (63).

Abstract: A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information.

Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.

Abstract: PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.

Abstract: PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.

Abstract: A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N1) is electrically connected to a terminal (P2) between the drains of PMOS and NMOS transistors (MP2, MN2). As a target capacitance forming part, a coupling capacitance (Cc) is formed between the node (N1) and a node (N2). The node (N2) is connected to a pad (58) through the terminal (P2) and an NMOS transistor (MN3), and a node (N3) is connected to a terminal (P3) between the drains of PMOS and NMOS transistors (MP1, MN1). A reference capacitance (Cref) is formed at the node (N3) as a dummy capacitance. Currents (Ir, It) supplied from a power source to the nodes (N3, N1) are measured with current meters (61, 62), respectively and a current (Im) induced from the node (N2) and flowing to a ground level is measured with a current meter (63).

Abstract: An electromagnetic field analyzer (11) finally replaces a fill metal pattern in a wiring pattern library (32) with an insulator of high dielectric constant, and stores, in a capacitance value data base (33), parasitic capacitance value information in which values of parasitic capacitances parasiting the insulator and fill metal patterns are in correspondence. A regression analyzer (12) stores, in a regression equation data base (36), regression equation information for deriving parasitic capacitance values from the fill metal patterns and associated size information. A parasitic capacitance extractor (13) obtains values of parasitic capacitances parasiting the replacing insulator for outputting parasitic capacitance information (37) while applying a regression equation of the regression equation information to the size information associated with the fill metal patterns.

Abstract: A semiconductor circuit extraction apparatus: detects the uppermost wiring layer of a cell; carries out virtual wiring conductor routing on all tracks of a cell-top wiring layer directly overlying the uppermost wiring layer of the cell; extracts parasitic capacitances of all the wiring conductors including those virtually routed; and calculates the delay time of placement/routing data in accordance with the extracted parasitic capacitances to provide highly accurate delay information library data.

Abstract: In a semiconductor device provided with a plurality of standard cells each comprising an input terminal and MOS transistors, a diffused region having a substantially negligibly small resistance is formed in a semiconductor substrate, and the input terminal of the standard cell and gates of the MOS transistors are connected through the diffused region. Also, a diffused region is formed under the input terminal in the substrate, and the input terminal is connected to the diffused region. In a modification, another standard cell is formed by forming a diffused region and a metal layer connected to the diffused region on the substrate, and the another standard cell is connected to the input terminal.

Abstract: A clock signal analysis device (100, 200, 300) has a pre-processing section (4) for reading circuit connection information, transistor characteristic information, and control information stored in memories (1, 2, 3) and for editing those information to be used for a simulation by a simulation execution section (5). The simulation execution section (5) executes a simulation of circuit operation, and then an after-processing section (6) calculates a delay value from a clock signal input node to a clock signal terminal node, a difference between delay values of clock signal terminal nodes, a rising time, a falling time of the clock signal and displays an analysis result by using a two-dimensional distribution map through a monitor (8).

Abstract: A semiconductor circuit extraction apparatus: detects the uppermost wiring layer of a cell; carries out virtual wiring conductor routing on all tracks of a cell-top wiring layer directly overlying the uppermost wiring layer of the cell; extracts parasitic capacitances of all the wiring conductors including those virtually routed; and calculates the delay time of placement/routing data in accordance with the extracted parasitic capacitances to provide highly accurate delay information library data, which is made usable in an autoplacement/routing apparatus and in a library distribution system.

Abstract: In a semiconductor device provided with a plurality of standard cells each comprising an input terminal and MOS transistors, a diffused region having a substantially negligibly small resistance is formed in a semiconductor substrate, and the input terminal of the standard cell and gates of the MOS transistors are connected through the diffused region. Also, a diffused region is formed under the input terminal in the substrate, and the input terminal is connected to the diffused region. In a modification, another standard cell is formed by forming a diffused region and a metal layer connected to the diffused region on the substrate, and the another standard cell is connected to the input terminal.