Patents by Inventor Toshimasa Itooka

Toshimasa Itooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8274125
    Abstract: An insulation is provided in a portion surrounding a light receiving portion in a semiconductor element, and a sealing resin is provided around the insulation, thereby warping the insulation outward when viewed from the light receiving portion to prevent diffuse light from returning to the light receiving portion of the semiconductor element.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: September 25, 2012
    Assignee: Panasonic Corporation
    Inventors: Junya Furuyashiki, Noriyuki Yoshikawa, Toshiyuki Fukuda, Toshimasa Itooka, Hiroki Utatsu
  • Publication number: 20110001208
    Abstract: An insulation is provided in a portion surrounding a light receiving portion in a semiconductor element, and a sealing resin is provided around the insulation, thereby warping the insulation outward when viewed from the light receiving portion to prevent diffuse light from returning to the light receiving portion of the semiconductor element.
    Type: Application
    Filed: February 26, 2009
    Publication date: January 6, 2011
    Inventors: Junya Furuyashiki, Noriyuki Yoshikawa, Toshiyuki Fukuda, Toshimasa Itooka, Hiroki Utatsu
  • Publication number: 20100308468
    Abstract: In a semiconductor device made of a plurality of materials, if the device is fabricated through a step of cutting the bonded plurality of materials, a boundary line of the plurality of materials is exposed on a cutting plane. Internal stress in the cutting remains at this boundary line to allow moisture and corrosive gas to easily enter into the device. In order to reduce the entrance of the moisture, the gas, and the like, the boundary appearing on the cutting plane is covered by a covering layer. At this time, partial cutting exposing the boundary line and not separating semiconductor devices are performed so that the covering layer can be formed with the plurality of semiconductor devices attached to the substrate.
    Type: Application
    Filed: March 2, 2009
    Publication date: December 9, 2010
    Inventors: Noriyuki Yoshikawa, Toshiyuki Fukuda, Junya Furuyashiki, Toshimasa Itooka, Hiroki Utatsu