Patents by Inventor Toshimitsu Tatsuka

Toshimitsu Tatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9693069
    Abstract: It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part determines the number of intra macroblocks to be allocated in each frame. A position determination part arranges the intra macroblocks at random positions in each frame. A coding part performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part, and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part, to thereby output compressed image data.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: June 27, 2017
    Assignee: MegaChips Corporation
    Inventors: Hiromu Hasegawa, Toshimitsu Tatsuka, Takeaki Komuro
  • Patent number: 9661333
    Abstract: An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter for quantization. The controller determines a quantization parameter of a currently target macroblock as an increase or decrease from a reference value, and determines the increase or decrease based on a difference between a target amount of code for a predetermined number of macroblocks fewer than a total number of macroblocks within one frame and a generated amount of code of the predetermined number of macroblocks processed immediately before. The controller can further determine the increase or decrease, based on pixel information of the currently target macroblock such as an activity evaluation value.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: May 23, 2017
    Assignee: MegaChips Corporation
    Inventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
  • Patent number: 9294783
    Abstract: In an image encoding device, a variable-length encoder encodes a quantized macro blocks and generates encoded data. The variable-length encoder forcefully encodes an end macro block of a line group composed of macro block lines, as a non-skipped macro block. Each of macro blocks which are to be encoded subsequent to the end macro block is encoded as a non-skipped macro block until an amount of codes of the encoded data including the end macro block reaches the smallest unit of transmission of the transmission part. As a result, the encoded data including the end macro block is transmitted to the image decoding device by the smallest unit of transmission.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 22, 2016
    Assignee: MegaChips Corporation
    Inventor: Toshimitsu Tatsuka
  • Publication number: 20160065971
    Abstract: It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part (12) determines the number of intra macroblocks to be allocated in each frame. A position determination part (13) arranges the intra macroblocks at random positions in each frame. A coding part (11) performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part (12), and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part (13), to thereby output compressed image data (22).
    Type: Application
    Filed: November 9, 2015
    Publication date: March 3, 2016
    Applicant: MegaChips Corporation
    Inventors: Hiromu HASEGAWA, Toshimitsu TATSUKA, Takeaki KOMURO
  • Publication number: 20150063470
    Abstract: In an image encoding device, a variable-length encoder encodes a quantized macro blocks and generates encoded data. The variable-length encoder forcefully encodes an end macro block of a line group composed of macro block lines, as a non-skipped macro block. Each of macro blocks which are to be encoded subsequent to the end macro block is encoded as a non-skipped macro block until an amount of codes of the encoded data including the end macro block reaches the smallest unit of transmission of the transmission part. As a result, the encoded data including the end macro block is transmitted to the image decoding device by the smallest unit of transmission.
    Type: Application
    Filed: January 15, 2013
    Publication date: March 5, 2015
    Applicant: MegaChips Corporation
    Inventor: Toshimitsu Tatsuka
  • Patent number: 8731312
    Abstract: It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A numerical value (Ftk) is generated from the lower-order six bits of the frame number (Ft) of a coding object frame. A numerical value (Fs) is generated by shifting the numerical value (Ftk) leftward by two bits. An exclusive OR of the numerical value (Ftk) and the numerical value (Fs) is calculated, to thereby generate a numerical value (A). A numerical value (Ytk) is generated from the lower-order six bits of the Y coordinate (Yt) of a coding object macroblock. The upper-order bits of the numerical value (Ytk) and the lower-order bits thereof are inverted, to thereby generate a numerical value (Yr). Further, an exclusive OR of the numerical value (Yr) and the numerical value (A) is calculated, to thereby generate a numerical value (B).
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 20, 2014
    Assignee: MegaChips Corporation
    Inventors: Hiromu Hasegawa, Toshimitsu Tatsuka
  • Patent number: 8712176
    Abstract: An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: April 29, 2014
    Assignee: MegaChips Corporation
    Inventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
  • Patent number: 8699807
    Abstract: An image coding apparatus calculates the activity of each macroblock. All the macroblocks of block lines are set as intra-candidate macroblocks (intra-candidate MBs) which are candidates for intra coding. Every other macroblock is set as an intra-candidate MB in block lines. One of the intra-candidate MBs in each block line, which has the minimum activity, is determined as an intra macroblock of a frame. The macroblock determined as the intra MB is changed from the intra-candidate MB to an intra-forbidden macroblock. After changing the setting of the intra-candidate MBs, intra macroblocks are determined for a frame inputted subsequent to the frame.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: April 15, 2014
    Assignee: MegaChips Corporation
    Inventors: Toshimitsu Tatsuka, Hiromu Hasegawa
  • Publication number: 20130195179
    Abstract: An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter in the quantization. The controller determines a quantization parameter of a currently target macroblock, based on a difference between a target amount of code for a specified number of macroblocks and an amount of code generated for a predetermined number of macroblocks processed immediately before. The controller variably sets the specified number.
    Type: Application
    Filed: August 26, 2011
    Publication date: August 1, 2013
    Applicant: MegaChips Corporation
    Inventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
  • Publication number: 20130028534
    Abstract: An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame, is obtained.
    Type: Application
    Filed: November 29, 2010
    Publication date: January 31, 2013
    Applicant: MegaChips Corporation
    Inventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada
  • Publication number: 20120321207
    Abstract: It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A numerical value (Ftk) is generated from the lower-order six bits of the frame number (Ft) of a coding object frame. A numerical value (Fs) is generated by shifting the numerical value (Ftk) leftward by two bits. An exclusive OR of the numerical value (Ftk) and the numerical value (Fs) is calculated, to thereby generate a numerical value (A). A numerical value (Ytk) is generated from the lower-order six bits of the Y coordinate (Yt) of a coding object macroblock. The upper-order bits of the numerical value (Ytk) and the lower-order bits thereof are inverted, to thereby generate a numerical value (Yr). Further, an exclusive OR of the numerical value (Yr) and the numerical value (A) is calculated, to thereby generate a numerical value (B).
    Type: Application
    Filed: February 24, 2011
    Publication date: December 20, 2012
    Applicant: MegaChips Corporation
    Inventors: Hiromu Hasegawa, Toshimitsu Tatsuka
  • Publication number: 20120307881
    Abstract: A device preventing degradation of image quality caused by coding of a moving image. A compression coder performs compression coding on image data of respective pictures constituting an input moving image to generate inter-coded data or intra-coded data, and outputs the coded data to a wire or wireless transmission line. In a case of causing the compression coder to generate the inter-coded data, a controller sets a code amount equal to or smaller than a maximum code amount given by a value obtained by multiplying an upper limit transmission rate of a transmission line and a permissible time allocated per picture based on a picture rate of the input moving image. Meanwhile, in a case of causing the compression coder to generate the intra-coded data, the controller sets a code amount larger than the maximum code amount and equal to or smaller than N-times (N is an integer equal to or larger than two) the maximum code amount.
    Type: Application
    Filed: November 9, 2010
    Publication date: December 6, 2012
    Applicant: MegaChips Corporation
    Inventors: Takashi Sawada, Takeaki Komuro, Toshimitsu Tatsuka
  • Publication number: 20120308151
    Abstract: An image coding apparatus calculates the activity of each macroblock. All the macroblocks of block lines are set as intra-candidate macroblocks (intra-candidate MBs) which are candidates for intra coding. Every other macroblock is set as an intra-candidate MB in block lines. One of the intra-candidate MBs in each block line, which has the minimum activity, is determined as an intra macroblock of a frame. The macroblock determined as the intra MB is changed from the intra-candidate MB to an intra-forbidden macroblock. After changing the setting of the intra-candidate MBs, intra macroblocks are determined for a frame inputted subsequent to the frame.
    Type: Application
    Filed: January 6, 2011
    Publication date: December 6, 2012
    Applicant: MegaChips Corporation
    Inventors: Toshimitsu Tatsuka, Hiromu Hasegawa
  • Publication number: 20120294361
    Abstract: An image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part determines the number of intra macroblocks to be allocated in each frame. A position determination part arranges the intra macroblocks at random positions in each frame. A coding part performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part, and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part, to thereby output compressed image data.
    Type: Application
    Filed: January 18, 2011
    Publication date: November 22, 2012
    Applicant: MegaChips Corporation
    Inventors: Hiromu Hasegawa, Toshimitsu Tatsuka, Takeaki Komuro
  • Publication number: 20120287990
    Abstract: An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter for quantization. The controller determines a quantization parameter of a currently target macroblock as an increase or decrease from a reference value, and determines the increase or decrease based on a difference between a target amount of code for a predetermined number of macroblocks fewer than a total number of macroblocks within one frame and a generated amount of code of the predetermined number of macroblocks processed immediately before. The controller can further determine the increase or decrease, based on pixel information of the currently target macroblock such as an activity evaluation value.
    Type: Application
    Filed: November 29, 2010
    Publication date: November 15, 2012
    Applicant: MegaChips Corporation
    Inventors: Toshimitsu Tatsuka, Hiromu Hasegawa, Takeaki Komuro, Masato Yamada