Abstract: A semiconductor apparatus is equipped with an internal circuit (201) including a semiconductor element (202)(203) and a protection circuit (101) including a semiconductor (102)(103) for protecting the internal circuit (201) against damage from electrostatic discharge (ESD). The semiconductor elements (102)(103) (202)(203) constituting the internal circuit (201) and the protection circuit (101) include an impurity diffusion region (7)(8) connected by an external terminal and a guard band region (6)(5) formed near the impurity diffusion region (7)(8), respectively. A shortest distance (102L)(103L) between the impurity diffusion region (7)(8) and the guard band region (6)(5) in the semiconductor element (102)(103) of the protection circuit (101) is set to be shorter than a shortest distance (202L)(203L) between the impurity diffusion region (7)(8) and the guard band region (6)(5) in the semiconductor element (202)(203) of the internal circuit (201).

Abstract: A CMOS semiconductor device having a triple well structure which can block latch-up by preventing parasitic thyristors from turning on is offered with reduced layout area. The CMOS semiconductor device includes a P-type silicon substrate, a first and a second deep N-type wells formed in a surface of the P-type silicon substrate and separated from each other, a P-type well formed in the first deep N-type well, a shallow N-type well formed in the second deep N-type well, an N-channel type MOS transistor formed on a surface of the P-type well and a P-channel type MOS transistor formed on a surface of the shallow N-type well.

Abstract: This invention provides an electrostatic damage protection device which can protects a device to be protected enough from an electrostatic damage and prevents damages of protection transistors themselves. A N-channel type first MOS transistor and a N-channel type second MOS transistor serving as protection transistors are connected in series between an output terminal and a ground potential. On the other hand, a P-channel type third MOS transistor and a P-channel type fourth MOS transistor serving as protection transistors are connected in series between a high power supply potential and the output terminal. These first, second, third, and fourth MOS transistors are formed of low withstand voltage MOS transistors.

Abstract: A semiconductor apparatus is equipped with an internal circuit (201) including a semiconductor element (202)(203) and a protection circuit (101) including a semiconductor (102)(103) for protecting the internal circuit (201) against damage from electrostatic discharge (ESD). The semiconductor elements (102)(103) (202)(203) constituting the internal circuit (201) and the protection circuit (101) include an impurity diffusion region (7)(8) connected by an eternal terminal and a guard band region (6)(5) formed near the impurity diffusion region (7)(8), respectively. A shortest distance (102L)(103L) between the impurity diffusion region (7)(8) and the guard band region (6)(5) in the semiconductor element (102)(103) of the protection circuit (101) is set to be shorter than a shortest distance (202L)(203L) between the impurity diffusion region (7)(8) and the guard band region (6)(5) in the semiconductor element (202)(203) of the internal circuit (201).

Abstract: This invention provides an electrostatic damage protection device which can protects a device to be protected enough from an electrostatic damage and prevents damages of protection transistors themselves. A N-channel type first MOS transistor and a N-channel type second MOS transistor serving as protection transistors are connected in series between an output terminal and a ground potential. On the other hand, a P-channel type third MOS transistor and a P-channel type fourth MOS transistor serving as protection transistors are connected in series between a high power supply potential and the output terminal. These first, second, third, and fourth MOS transistors are formed of low withstand voltage MOS transistors.

Abstract: A CMOS semiconductor device having a triple well structure which can block latch-up by preventing parasitic thyristors from turning on is offered with reduced layout area. The CMOS semiconductor device includes a P-type silicon substrate, a first and a second deep N-type wells formed in a surface of the P-type silicon substrate and separated from each other, a P-type well formed in the first deep N-type well, a shallow N-type well formed in the second deep N-type well, an N-channel type MOS transistor formed on a surface of the P-type well and a P-channel type MOS transistor formed on a surface of the shallow N-type well.