Patents by Inventor Toshio Nagata

Toshio Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070054692
    Abstract: Methods and apparatus to perform noise estimation for frequency-domain equalizers of high-speed downlink packet access (HSDPA) receivers are disclosed. An example method comprises measuring a total power associated with a code division multiple access (CDMA) signal received through a plurality of multipaths, measuring a plurality of channel responses for respective ones of the plurality of multipaths, measuring a plurality of noise plus inter-path interference powers for the respective ones of the plurality of multipaths, and estimating an additive noise power for the received CDMA signal based on the total power, the plurality of channel responses and the plurality of noise plus inter-path interference powers.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 8, 2007
    Inventors: Junhong Nie, Yuan Li, Juncheng Liu, Toshio Nagata, Raied Salem
  • Publication number: 20070053416
    Abstract: Methods and apparatus to perform closed-loop transmit diversity with frequency-domain equalizers in high-speed downlink packet access (HSDPA) receivers are disclosed. An example method comprises receiving a first signal representative of a first code division multiple access (CDMA) signal received from a first transmit antenna and a second signal representative of a second CDMA signal received from a second transmit antenna, computing a first channel estimate for a first path from the first transmit antenna to the receiver, computing a second channel estimate for a second path from the second transmit antenna to the receiver, and computing a frequency-domain equalizer (FDE) coefficient for the first path based on the first and the second channel estimates.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 8, 2007
    Inventors: Yuan Li, Toshio Nagata, Raied Salem
  • Publication number: 20070053417
    Abstract: Methods and apparatus to perform fractional-spaced channel estimation for frequency-domain equalizers in high-speed downlink packet access (HSDPA) receivers are disclosed. An example method comprises computing a first fractionally-spaced time-domain channel estimate from an oversampled CDMA signal, and computing a first chip-interval frequency-domain equalizer (FDE) coefficient from the first fractionally-spaced channel estimate.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 8, 2007
    Inventors: Toshio Nagata, Yuan Li, Raied Salem
  • Publication number: 20070004155
    Abstract: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during deposition. In a third embodiment, initial temperature of the CVD device is kept at about 400° C., whereby the start of natural oxidation of the deposition surface is prevented and production circumstances of the semiconductor element is not deteriorated. Then, the CVD device is heated up to CVD temperature of about 750° C. or about 650° C., to deposit oxide.
    Type: Application
    Filed: August 12, 2005
    Publication date: January 4, 2007
    Inventor: Toshio Nagata
  • Patent number: 7072926
    Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability figure (logarithm of ratio of maximum survivor path metric minus minimum survivor path metric divided by 0 state path metric minus minimum survivor path metric) with a small lookup table plus simple logic.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: July 4, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Toshio Nagata, Mitsuhiko Yagyu
  • Publication number: 20060034352
    Abstract: Methods and apparatus to facilitate improve code division multiple access (CDMA) receivers are disclosed. An example method disclosed herein comprises: receiving a signal containing first portions that are based on known data and second portions that are based on unknown data; generating a training signal, from the received signal, that substantially represents one or more of the first portions; adapting filter coefficients using the training signal; and equalizing the received signal using the adapted filter coefficients.
    Type: Application
    Filed: June 13, 2005
    Publication date: February 16, 2006
    Inventors: Ashwin Sampath, Toshio Nagata
  • Patent number: 6953966
    Abstract: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during deposition. In a third embodiment, initial temperature of the CVD device is kept at about 400° C., whereby the start of natural oxidation of the deposition surface is prevented and production circumstances of the semiconductor element is not deteriorated. Then, the CVD device is heated up to CVD temperature of about 750° C. or about 650° C., to deposit oxide.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: October 11, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshio Nagata
  • Patent number: 6830974
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a first film of silicon nitride or silicon oxynitride on a polysilicon layer, forming a second film of silicon oxide on the first film by chemical vapor deposition, and oxygen-annealing the second film to form a tunnel oxide film. The presence of the silicon nitride or silicon oxynitride film enables an annealing process with a high oxidation capability to be used without oxidizing the polysilicon layer. The leakage of unwanted current through the tunnel oxide film can thereby be reduced, improving the data retention characteristics of devices such as flash memories.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: December 14, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshio Nagata
  • Publication number: 20040082129
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a first film of silicon nitride or silicon oxynitride on a polysilicon layer, forming a second film of silicon oxide on the first film by chemical vapor deposition, and oxygen-annealing the second film to form a tunnel oxide film. The presence of the silicon nitride or silicon oxynitride film enables an annealing process with a high oxidation capability to be used without oxidizing the polysilicon layer. The leakage of unwanted current through the tunnel oxide film can thereby be reduced, improving the data retention characteristics of devices such as flash memories.
    Type: Application
    Filed: June 27, 2003
    Publication date: April 29, 2004
    Inventor: Toshio Nagata
  • Patent number: 6605779
    Abstract: The present invention protects a thin wire connection from oscillation of a resin protecting an electronic circuit module from vibration, impact, and corrosion. An electronic control unit including an electronic circuit module in which a bare chip is mounted on a circuit board and a case for housing the module, is provided, wherein the case is filled with a potting gel to protect the module. The bare chip, including its wire connection to the circuit board, is sealed in advance with a gelatinous resin having thixotropy prior to hardening. The gelatinous substance cures to form a hardened inner layer which has a penetration that is lower than that of the filled potting gel after hardening, and functions to eliminate or substantially reduce the affect of viscoelastic oscillation of the outer layer on the bare chip and the wire connection.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: August 12, 2003
    Assignees: Aisin Aw Co., Ltd., Kyocera Corporation
    Inventors: Hiroki Takata, Kenji Suzuki, Naoto Ogasawara, Toshio Nagata
  • Publication number: 20030143844
    Abstract: As the first method, provided is using Tetraethyl Orthosilicate Si(OC2H5)4 at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. As the second method, provided is annealing in sparse oxygen gas atmosphere after deposition, to mend crystal defects occurred during deposition. As the third method, provided is keeping initial temperature of CVD device in the temperature (about 400° C.) in which natural oxidation of deposition starting surface is prevented and production circumstance of semiconductor element is not deteriorated, then, heating up to CVD temperature (about 750° C. or about 650° C.), to deposit oxide.
    Type: Application
    Filed: September 26, 2002
    Publication date: July 31, 2003
    Inventor: Toshio Nagata
  • Patent number: 6524968
    Abstract: A method for forming an insulating film is provided which is capable of inhibiting spontaneous growth of a silicon oxide film formed on a silicon substrate and an increase in thickness of a film caused by exposure to an atmosphere. After having allowed a silicon dioxide layer with a predetermined thickness to grow on a surface of a silicon crystal, a surface of the silicon dioxide is exposed to organic gas containing no hydroxyl group or is exposed to ammonia gas.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: February 25, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masashi Takahashi, Toshio Nagata, Yoshirou Tsurugida, Takashi Ohsako, Hirotaka Mori, Akihiko Ohara, Hidetsugu Uchida, Hiroaki Uchida, Katsuji Yoshida, Masahiro Takahashi
  • Publication number: 20030014456
    Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability logarithm function with a small lookup table plus simple logic.
    Type: Application
    Filed: June 7, 2002
    Publication date: January 16, 2003
    Inventors: Toshio Nagata, Mitsuhiko Yagyu
  • Publication number: 20030007580
    Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability logarithm function with a small lookup table plus simple logic.
    Type: Application
    Filed: June 7, 2002
    Publication date: January 9, 2003
    Inventors: Toshio Nagata, Mitsuhiko Yagyu
  • Publication number: 20030008523
    Abstract: A method for forming an insulating film is provided which is capable of inhibiting spontaneous growth of a silicon oxide film formed on a silicon substrate and an increase in thickness of a film caused by exposure to an atmosphere.
    Type: Application
    Filed: October 5, 2001
    Publication date: January 9, 2003
    Inventors: Masashi Takahashi, Toshio Nagata, Yoshirou Tsurugida, Takashi Ohsako, Hirotaka Mori, Akihiko Ohara, Hidetsugu Uchida, Hiroaki Uchida, Katsuji Yoshida, Masahiro Takahashi
  • Publication number: 20020079119
    Abstract: The present invention protects a thin wire connection from oscillation of a resin protecting an electronic circuit module from vibration, impact, and corrosion. An electronic control unit comprising an electronic circuit module in which a bare chip is mounted on a circuit board and a case for housing the module, is provided, wherein the case is filled with a potting gel to protect the module. The bare chip, including its wire connection to the circuit board, is sealed in advance with a gelatinous resin having thixotropy prior to hardening. The gelatinous substance cures to form a hardened inner layer which has a penetration that is lower than that of the filled potting gel after hardening, and functions to eliminate or substantially reduce the affect of viscoelastic oscillation of the outer layer on the bare chip and the wire connection.
    Type: Application
    Filed: October 5, 2001
    Publication date: June 27, 2002
    Inventors: Hiroki Takata, Kenji Suzuki, Naoto Ogasawara, Toshio Nagata
  • Patent number: 6404121
    Abstract: An explosion-proof tape is wound on an outer circumference of a panel portion of a cathode-ray tube and a metal band is shrink-fitted on the tape. The tape is composed of a support having at least a layer composed of propylene polymer with a propylene content of not less than 40 weight % or styrene polymer with a styrene content of not less than 50 weight % and an adhesive layer formed on one surface of the support in a manner so that a plurality of fibers with a softening point of not lower than 200° C. are buried in the adhesive layer in a lengthwise direction of the tape. An explosion-proof structure of a cathode-ray tube, wherein a metal band is shrink-fitted on an outer circumference of a panel portion of a cathode-ray tube, through a layer which is formed by winding such an explosion-proof tape as mentioned above, through its adhesive layer.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: June 11, 2002
    Assignees: Nitto Denko Corporation, Sony Corporation
    Inventors: Yoichiro Goto, Koichi Nakamura, Hiroshi Yamamoto, Kazukuni Tamaki, Toshio Nagata
  • Patent number: 6399494
    Abstract: A method of making a semiconductor device comprises forming a gate electrode on a semiconductor substrate, forming a diffusion layer in the semiconductor substrate, forming a first SiO2 film on a bottom surface of the semiconductor substrate and second SiO2 film on an upper surface of the semiconductor substrate, removing the second SiO2 film, forming a CoSi2 film on the diffusion, and removing an undesired cobalt from the first SiO2 film.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: June 4, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshio Nagata
  • Publication number: 20020064950
    Abstract: A method of making a semiconductor device comprises forming a gate electrode on a semiconductor substrate, forming a diffusion layer in the semiconductor substrate, forming a first SiO2 film on a bottom surface of the semiconductor substrate and second SiO2 film on an upper surface of the semiconductor substrate, removing the second SiO2 film, forming a CoSi2 film on the diffusion, and removing an undesired cobalt from the first SiO2 film.
    Type: Application
    Filed: September 5, 2001
    Publication date: May 30, 2002
    Inventor: Toshio Nagata
  • Patent number: 6319763
    Abstract: A lower capacitor electrode is formed on an interlayer dielectric, and then a resultant specimen is subjected to reduction and thermal nitriding in an ammonia gas atmosphere in a deposition chamber wherein pressure has been reduced to a range from 533 Pa to 1333 Pa. A silicon nitride film is then formed on the lower electrode and the interlayer dielectric. A time for carrying out the reduction and thermal nitriding is longer than a film thickness saturation time of the silicon nitride film formed on the interlayer dielectric.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: November 20, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Makoto Nakazawa, Toshio Nagata