Patents by Inventor Toshio Sasaki
Toshio Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20100090282Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.Type: ApplicationFiled: December 17, 2009Publication date: April 15, 2010Inventors: OSAMU OZAWA, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi
-
Publication number: 20100090113Abstract: To retrieve information from an optical storage medium having a recording layer in which binary information is recorded in a form of presence or absence of a fluorescing property, the recording layer is illuminated with a light beam in a linearly polarized state, to induce fluorescence in the recording layer. Fluorescent light is isolated from light reflected in the optical storage medium by a polarized light separation element attenuating a linearly polarized component (including the light reflected in the optical storage medium) of the light coming from the optical storage medium, and the fluorescent light derived from the induced fluorescence is detected by a photosensor, which outputs a signal bearing the binary information recorded in the recording layer.Type: ApplicationFiled: October 14, 2009Publication date: April 15, 2010Applicant: FUJIFILM CORPORATIONInventor: Toshio SASAKI
-
Publication number: 20100061212Abstract: The present invention is to provide a method for treating an optical recording medium including irradiating a recording layer, which has recorded information, with a treatment light through a light diffusion member having a haze of 70% to 100%, wherein the optical recording medium contains at least the recording layer which records information using holography, and a device for treating an optical recording medium containing a light source for the treatment light, and the light diffusion member having a haze of 70% to 100% and disposed between the light source and the optical recording medium, wherein the recording layer is irradiated with the treatment light through the light diffusion member from the light source. The preferred aspects are that a half width of wavelength for an energy intensity of the treatment light is 5 nm to 700 nm; and the optical recording medium is a write-once read-many optical recording medium.Type: ApplicationFiled: December 18, 2006Publication date: March 11, 2010Applicant: FUJIFILM CORPORATIONInventors: Makoto Kamo, Yoshihisa Usami, Toshio Sasaki
-
Publication number: 20100034044Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.Type: ApplicationFiled: October 16, 2009Publication date: February 11, 2010Inventors: TOSHIO SASAKI, Yoshihiko YASU, Takashi KURAISHI, Ryo MORI
-
Patent number: 7652333Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.Type: GrantFiled: December 21, 2006Date of Patent: January 26, 2010Assignee: Renesas Technology Corp.Inventors: Osamu Ozawa, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi
-
Patent number: 7623364Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.Type: GrantFiled: January 17, 2008Date of Patent: November 24, 2009Assignee: Renesas Technology Corp.Inventors: Toshio Sasaki, Yoshihiko Yasu, Takashi Kuraishi, Ryo Mori
-
Publication number: 20090108422Abstract: The present invention can supply power for each circuit section by separating and connecting bus-bar (21d) for each circuit section inside the semiconductor chip (22), and, in addition, can increase the number of pads (22a) for power supply or can use the lead (21a) conventionally used for power supply for signals by further making the best of the characteristics that enable the connection to bus-bar (21d) irrespective of the inner lead (21b) pitch, by making the pitch of the pad (22a) smaller than the pitch of the inner lead (21b), or by forming the pad (22a) in a zigzag arrangement.Type: ApplicationFiled: December 21, 2008Publication date: April 30, 2009Inventors: Toshio SASAKI, Fujio ITO, Hiromichi SUZUKI
-
Publication number: 20090079465Abstract: The present invention aims to make each power shutdown area appropriate. Cell areas each comprising a plurality of core cells arranged therein, and power switches disposed corresponding to the respective cell areas are provided. A plurality of power shutdown areas are respectively formed in units of the core cells. In each power shutdown area, power shutdown is enabled by the power switches corresponding to the power shutdown areas. Thus, the power shutdown areas can be set finely in the core cell units, and the appropriateness of each power shutdown area is achieved. With its appropriateness, a reduction in current consumption at standby is achieved.Type: ApplicationFiled: April 21, 2005Publication date: March 26, 2009Inventors: Toshio Sasaki, Yoshihiko Yasu, Ryo Mori, Koichiro Ishibashi, Yusuke Kanno
-
Publication number: 20090059763Abstract: The present invention provides a filter for optical recording medium capable of preventing diffuse reflection of an information beam and a reference beam from a reflective layer in the optical recording medium and preventing occurrence of noise without causing shift in selective reflection wavelength, and distortion in a reproduced image even when an angle of incidence is changed, and an optical recording medium capable of recording a high density image by using the filter. Specifically, the present invention relates to the optical recording medium containing a first substrate, a recording layer which records information by utilizing holography, an optical compensation layer, a filter layer, and a second substrate, in this order, and the filter layer is a cholesteric liquid crystal layer.Type: ApplicationFiled: February 2, 2006Publication date: March 5, 2009Applicant: FujiFilm CorporationInventors: Koh Kamada, Ichiro Amimori, Mitsuyoshi Ichihashi, Toshio Sasaki
-
Publication number: 20090051988Abstract: A holographic recording medium includes at least two substrates, and a recording layer provided between the substrates. The recording layer has a property such that an average refractive index lowers as irradiation with a beam proceeds. In the recording layer, an optical compensation rate C that is defined by C=(1?(n2/n1))/? satisfies 0.8?C?1.0, where ? is a rate of thickness change of the recording layer before and after recording, n1 is an average refractive index before recording, and n2 is an average refractive index after recording.Type: ApplicationFiled: August 18, 2008Publication date: February 26, 2009Applicant: FUJIFILM CORPORATIONInventors: Toshio SASAKI, Satoru Yamada, Hiroyuki Suzuki, Yoshihisa Usami, Makoto Kamo
-
Patent number: 7482699Abstract: The present invention can supply power for each circuit section by separating and connecting bus-bar (21d) for each circuit section inside the semiconductor chip (22), and, in addition, can increase the number of pads (22a) for power supply or can use the lead (21a) conventionally used for power supply for signals by further making the best of the characteristics that enable the connection to bus-bar (21d) irrespective of the inner lead (21b) pitch, by making the pitch of the pad (22a) smaller than the pitch of the inner lead (21b), or by forming the pad (22a) in a zigzag arrangement.Type: GrantFiled: May 16, 2003Date of Patent: January 27, 2009Assignee: Renesas Technology Corp.Inventors: Toshio Sasaki, Fujio Ito, Hiromichi Suzuki
-
Publication number: 20080311703Abstract: A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.Type: ApplicationFiled: August 19, 2008Publication date: December 18, 2008Inventors: Fujio Ito, Hiromichi Suzuki, Toshio Sasaki
-
Publication number: 20080258177Abstract: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.Type: ApplicationFiled: April 14, 2008Publication date: October 23, 2008Inventors: Hiroyuki IKEDA, Toshio Sasaki, Akinobu Watanabe, Toshio Yamada, Akihisa Uchida
-
Publication number: 20080254374Abstract: The present invention provides a holographic recording composition and a holographic recording medium comprising a recording layer formed with the holographic recording composition. The holographic recording composition comprises a bifunctional or greater isocyanate, a polyfunctional alcohol comprising a bifunctional alcohol and a trifunctional or greater alcohol, a titanocene-based radical polymerization initiator, a bifunctional or greater acrylate monomer, and an amidine salt denoted by General Formula (1). In General Formula (1), R1, R2, and R3 each independently denote an alkyl group, aryl group, amino group, or acyl group, R1 and R2 may be bonded together to form a ring, R2 and R3 may be bonded together to form a ring, and A? denotes an anion.Type: ApplicationFiled: April 3, 2008Publication date: October 16, 2008Applicant: FUJIFILM CorporationInventors: Satoru YAMADA, Makoto Kamo, Toshio Sasaki
-
Publication number: 20080239780Abstract: A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.Type: ApplicationFiled: January 17, 2008Publication date: October 2, 2008Inventors: Toshio SASAKI, Yoshihiko YASU, Takashi KURAISHI, Ryo MORI
-
Publication number: 20080219082Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: ApplicationFiled: March 11, 2008Publication date: September 11, 2008Inventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
-
Publication number: 20080204838Abstract: A fixing apparatus and a fixing method are disclosed for performing a fixing process on a holographic recording medium with an optically recordable recording layer. The fixing apparatus includes a light source which illuminates the recording layer with fixing light, and at least one reflecting mirror which reflects the fixing light passing through the recording layer and makes the fixing light go back again toward the recording layer.Type: ApplicationFiled: February 28, 2008Publication date: August 28, 2008Applicant: FUJIFILM CORPORATIONInventor: Toshio SASAKI
-
Patent number: 7413930Abstract: A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.Type: GrantFiled: August 29, 2003Date of Patent: August 19, 2008Assignee: Renesas Technology Corp.Inventors: Fujio Ito, Hiromichi Suzuki, Toshio Sasaki
-
Patent number: 7366016Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.Type: GrantFiled: January 25, 2007Date of Patent: April 29, 2008Assignee: Solid State Storage Solutions, LLCInventors: Masataka Kato, Tetsuo Adachi, Toshihiro Tanaka, Toshio Sasaki, Hitoshi Kume, Katsutaka Kimura
-
Publication number: 20080054894Abstract: The invention provides a magnetic detection device having excellent thermal resistance and water resistance by changing a configuration of layers of an insulating protection layer covering a magnetic detection element. A magnetic detection element is covered with an insulating protection layer, and the insulating protection layer has an alumina layer covering the magnet detection element and a silica layer covering the alumina layer. According to the embodiment, thermal resistance and water resistance can be properly improved, and therefore a magnetic detection device having excellent magnetic sensitivity and a high reliability can be realized without degrading characteristics of the magnetic detection device.Type: ApplicationFiled: February 26, 2007Publication date: March 6, 2008Applicant: ALPS ELECTRIC CO., LTD.Inventors: Toshio Sasaki, Kiyoshi Sato, Ichiro Tokunaga