Patents by Inventor Toshio Sugano
Toshio Sugano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190103152Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: ApplicationFiled: December 3, 2018Publication date: April 4, 2019Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Patent number: 10147479Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: GrantFiled: June 4, 2018Date of Patent: December 4, 2018Assignee: Longitude Semiconductor S.a.r.l.Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Publication number: 20180286472Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: ApplicationFiled: June 4, 2018Publication date: October 4, 2018Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Patent number: 10049722Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.Type: GrantFiled: September 28, 2017Date of Patent: August 14, 2018Assignee: Micron Technology, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
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Publication number: 20180197595Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.Type: ApplicationFiled: September 28, 2017Publication date: July 12, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
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Patent number: 9990982Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: GrantFiled: September 3, 2014Date of Patent: June 5, 2018Assignee: Longitude Semiconductor S.a.r.l.Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Patent number: 9837137Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.Type: GrantFiled: May 19, 2016Date of Patent: December 5, 2017Assignee: Micron Technology, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Patent number: 9805786Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.Type: GrantFiled: January 6, 2017Date of Patent: October 31, 2017Assignee: Micron Technology, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
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Patent number: 9570375Abstract: Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.Type: GrantFiled: June 25, 2013Date of Patent: February 14, 2017Assignee: Longitude Semiconductor S.a.r.l.Inventors: Atsushi Hiraishi, Toshio Sugano, Yasuhiro Takai
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Publication number: 20160267962Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.Type: ApplicationFiled: May 19, 2016Publication date: September 15, 2016Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Patent number: 9368185Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.Type: GrantFiled: October 7, 2014Date of Patent: June 14, 2016Assignee: Micron Technology, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Patent number: 9076500Abstract: Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.Type: GrantFiled: November 26, 2012Date of Patent: July 7, 2015Assignee: PS4 LUXCO S.A.R.L.Inventors: Fumiyuki Osanai, Toshio Sugano, Atsushi Hiraishi
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Publication number: 20150098289Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.Type: ApplicationFiled: October 7, 2014Publication date: April 9, 2015Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Patent number: 8988952Abstract: Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other.Type: GrantFiled: December 26, 2012Date of Patent: March 24, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Atsushi Hiraishi, Toshio Sugano, Seiji Narui, Yasuhiro Takai
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Patent number: 8922029Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.Type: GrantFiled: February 1, 2012Date of Patent: December 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Atsushi Hiraishi, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki
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Publication number: 20140369148Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: ApplicationFiled: September 3, 2014Publication date: December 18, 2014Inventors: Yoshinori MATSUI, Toshio SUGANO, Hiroaki IKEDA
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Patent number: 8854854Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: GrantFiled: June 28, 2012Date of Patent: October 7, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Publication number: 20140001639Abstract: Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.Type: ApplicationFiled: June 25, 2013Publication date: January 2, 2014Applicant: Elpida Memory, Inc.Inventors: Atsushi HIRAISHI, Toshio SUGANO, Yasuhiro TAKAI
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Patent number: 8422263Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.Type: GrantFiled: June 3, 2010Date of Patent: April 16, 2013Assignee: Elpida Memory, Inc.Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Fumiyuki Osanai, Masayuki Nakamura, Hiroki Fujisawa
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Patent number: RE45928Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: GrantFiled: August 7, 2014Date of Patent: March 15, 2016Assignee: PS4 Luxco S.a.r.l.Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda