Patents by Inventor Toshio Sugawa
Toshio Sugawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100025099Abstract: A circuit board is manufactured by filling a via-hole formed in an insulating substrate with conductive material, disposing conductive layers on both sides of the insulating substrate, and forming alloy of component material of the conductive material with component material of the conductive layers. In the circuit board, therefore, the conductive material filled in the via-hole formed in the insulating substrate is securely connected electrically as well as mechanically to the conductive layers on both sides of the insulating substrate with high reliability.Type: ApplicationFiled: August 7, 2009Publication date: February 4, 2010Applicant: Panasonic CorporationInventors: Toshio Sugawa, Satoshi Murakawa, Masaaki Hayama, Takeo Yasuho
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Publication number: 20090229862Abstract: A plurality of double-sided boards using a film are attached to each other with a paste coupling layer sandwiched therebetween. In the paste coupling layer, a conductive paste is filled into a through hole formed in provisionally hardened resin, which is hardened. At the same time, second wirings are electrically coupled to each other by using the hardened conductive paste filled in the through holes that have been previously formed in the paste coupling layer. Thus, it is possible to provide a thinned multilayer printed wiring board without using an adhesive.Type: ApplicationFiled: November 7, 2006Publication date: September 17, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tadashi Nakamura, Fumio Echigo, Shogo Hirai, Toshio Sugawa
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Patent number: 7423222Abstract: A circuit board is manufactured by filling a via-hole formed in an insulating substrate with conductive material, disposing conductive layers on both sides of the insulating substrate, and forming alloy of component material of the conductive material with component material of the conductive layers. In the circuit board, therefore, the conductive material filled in the via-hole formed in the insulating substrate is securely connected electrically as well as mechanically to the conductive layers on both sides of the insulating substrate with high reliability.Type: GrantFiled: January 11, 2002Date of Patent: September 9, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Sugawa, Satoshi Murakawa, Masaaki Hayama, Takeo Yasuho
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Publication number: 20080121416Abstract: In a case of multilayer circuit boards where a plurality of conventional films are used as insulating layers, the films are connected with each other using an adhesive, and therefore, the adhesive sometimes negatively affects reduction in thickness. Therefore, a plurality of two-sided boards with films used therein are pasted together with a paste connection layer interposed therebetween, the paste connection layer being configured such that through holes formed in a prepreg are filled in with a conductive paste which is then cured, and second wires are electrically connected with each other through the conductive paste with which the through holes formed in the paste connection layer in advance are filled in, and thus, a multilayer board can be provided without using an adhesive, and the entirety of the multilayer circuit board can be reduced in thickness.Type: ApplicationFiled: October 19, 2006Publication date: May 29, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shogo Hirai, Fumio Echigo, Tadashi Nakamura, Toshio Sugawa
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Patent number: 7291915Abstract: A circuit board includes an insulating substrate, a first conductive layer on the insulating substrate, a second conductive layer on the first conductive layer, and a third conductive layer covering the first conductive layer and the second conductive layer. The first conductive layer has a surface provided on the surface of the insulating substrate, and a surface having a width smaller than a width of the above surface. In this circuit board, the conductive layers have small impedances even if a high-frequency signal flows in the conductive layers.Type: GrantFiled: August 15, 2005Date of Patent: November 6, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Sugawa, Hideki Higashitani, Takumi Misaki
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Patent number: 7197820Abstract: A circuit board is provided in which peeling strength is prevented from decreasing and a connection resistance to a conductive material is prevented from increasing, though the contact area decreases when the circuit board has a copper foil. This circuit board has a metal film for covering a through hole on at least one surface of an insulating substrate having the through hole filled with the conductive material. An uneven layer with a thickness of 5 ?m or more is formed on a surface of the metal film, and a metal layer is formed on the opposite surface to the uneven layer.Type: GrantFiled: October 30, 2002Date of Patent: April 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Sugawa, Yoshihisa Takase
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Publication number: 20060054350Abstract: A circuit board includes an insulating substrate, a first conductive layer on the insulating substrate, a second conductive layer on the first conductive layer, and a third conductive layer covering the first conductive layer and the second conductive layer. The first conductive layer has a surface provided on the surface of the insulating substrate, and a surface having a width smaller than a width of the above surface. In this circuit board, the conductive layers have small impedances even if a high-frequency signal flows in the conductive layers.Type: ApplicationFiled: August 15, 2005Publication date: March 16, 2006Inventors: Toshio Sugawa, Hideki Higashitani, Takumi Misaki
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Publication number: 20040221449Abstract: A circuit board is manufactured by filling a via-hole formed in an insulating substrate with conductive material, disposing conductive layers on both sides of the insulating substrate, and forming alloy of component material of the conductive material with component material of the conductive layers. In the circuit board, therefore, the conductive material filled in the via-hole formed in the insulating substrate is securely connected electrically as well as mechanically to the conductive layers on both sides of the insulating substrate with high reliability.Type: ApplicationFiled: June 10, 2004Publication date: November 11, 2004Applicant: Matsushita Elec. Ind. Co. Ltd.Inventors: Toshio Sugawa, Satoshi Murakawa, Masaaki Hayama, Takeo Yasuho
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Patent number: 6748652Abstract: Through holes formed in an electrical insulating substrate having adhesive layers on its both surfaces are filled with a conductor. Then, supporting bases having wiring layers with a predetermined pattern are laminated on both the surfaces of the electrical insulating substrate, which are then heated and pressurized. After that, the supporting bases are removed, thus obtaining a circuit board in which the wiring layers have been embedded in the adhesive layers. The conductor within the through holes are compressed sufficiently, thus forming minute via holes with high reliability.Type: GrantFiled: March 26, 2003Date of Patent: June 15, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Daizou Andou, Toshio Sugawa, Tadashi Nakamura, Hideki Higashitani, Masahide Tsukamoto
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Publication number: 20040045738Abstract: The present invention provides a circuit board in which peeling strength is prevented from decreasing and connection resistance to conductive material is prevented from increasing, though the contact area decreases when the circuit board has a copper foil. This circuit board has metal film (105) for covering a through hole on at least one surface of insulating substrate (101) having the through hole filled with conductive material (104). Uneven layer (1069 with a thickness of 5 &mgr;m or more is formed on a surface of metal film (105), and a metal layer is formed on the opposite surface to uneven layer (106).Type: ApplicationFiled: July 9, 2003Publication date: March 11, 2004Inventors: Toshio Sugawa, Yoshihisa Takase
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Publication number: 20030180512Abstract: Through holes formed in an electrical insulating substrate having adhesive layers on its both surfaces are filled with a conductor. Then, supporting bases having wiring layers with a predetermined pattern are laminated on both the surfaces of the electrical insulating substrate, which are then heated and pressurized. After that, the supporting bases are removed, thus obtaining a circuit board in which the wiring layers have been embedded in the adhesive layers. The conductor within the through holes are compressed sufficiently, thus forming minute via holes with high reliability.Type: ApplicationFiled: March 26, 2003Publication date: September 25, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Daizou Andou, Toshio Sugawa, Tadashi Nakamura, Hideki Higashitani, Masahide Tsukamoto
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Patent number: 6565954Abstract: Through holes formed in an electrical insulating substrate having adhesive layers on its both surfaces are filled with a conductor. Then, supporting bases having wiring layers with a predetermined pattern are laminated on both the surfaces of the electrical insulating substrate, which are then heated and pressurized. After that, the supporting bases are removed, thus obtaining a circuit board in which the wiring layers have been embedded in the adhesive layers. The conductor within the through holes are compressed sufficiently, thus forming minute via holes with high reliability.Type: GrantFiled: December 1, 2000Date of Patent: May 20, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Daizou Andou, Toshio Sugawa, Tadashi Nakamura, Hideki Higashitani, Masahide Tsukamoto
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Patent number: 6532651Abstract: Through holes formed in an electrical insulating substrate having adhesive layers on its both surfaces are filled with a conductor. Then, supporting bases having wiring layers with a predetermined pattern are laminated on both the surfaces of the electrical insulating substrate, which are then heated and pressurized. After that, the supporting bases are removed, thus obtaining a circuit board in which the wiring layers have been embedded in the adhesive layers. The conductor within the through holes are compressed sufficiently, thus forming minute via holes with high reliability.Type: GrantFiled: February 15, 2000Date of Patent: March 18, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Daizou Andou, Toshio Sugawa, Tadashi Nakamura, Hideki Higashitani, Masahide Tsukamoto
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Publication number: 20030039811Abstract: A circuit board is manufactured by filling a via-hole formed in an insulating substrate with conductive material, disposing conductive layers on both sides of the insulating substrate, and forming alloy of component material of the conductive material with component material of the conductive layers. In the circuit board, therefore, the conductive material filled in the via-hole formed in the insulating substrate is securely connected electrically as well as mechanically to the conductive layers on both sides of the insulating substrate with high reliability.Type: ApplicationFiled: September 18, 2002Publication date: February 27, 2003Inventors: Toshio Sugawa, Satoshi Murakawa, Masaaki Hayama, Takeo Yasuho
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Publication number: 20010005545Abstract: Through holes formed in an electrical insulating substrate having adhesive layers on its both surfaces are filled with a conductor. Then, supporting bases having wiring layers with a predetermined pattern are laminated on both the surfaces of the electrical insulating substrate, which are then heated and pressurized. After that, the supporting bases are removed, thus obtaining a circuit board in which the wiring layers have been embedded in the adhesive layers. The conductor within the through holes are compressed sufficiently, thus forming minute via holes with high reliability.Type: ApplicationFiled: December 1, 2000Publication date: June 28, 2001Inventors: Daizou Andou, Toshio Sugawa, Tadashi Nakamura, Hideki Higashitani, Masahide Tsukamoto
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Patent number: 6197407Abstract: Through holes formed in an electrical insulating substrate having adhesive layers on its both surfaces are filled with a conductor. Then, supporting bases having wiring layers with a predetermined pattern are laminated on both the surfaces of the electrical insulating substrate, which are then heated and pressurized. After that, the supporting bases are removed, thus obtaining a circuit board in which the wiring layers have been embedded in the adhesive layers. The conductor within the through holes are compressed sufficiently, thus forming minute via holes with high reliability.Type: GrantFiled: May 4, 1999Date of Patent: March 6, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Daizou Andou, Toshio Sugawa, Tadashi Nakamura, Hideki Higashitani, Masahide Tsukamoto
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Patent number: 5844347Abstract: A SAW device comprising an inter-digital electrode capable of withstanding application of excessive electric power, while preventing an increase of insertion loss. The SAW device has an inter-digital electrode formed by alternating layers of aluminum films and conductive films, where the conductive films have an elastic constant greater than that of the aluminum films.Type: GrantFiled: August 29, 1996Date of Patent: December 1, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryoichi Takayama, Keizaburo Kuramasu, Toshio Sugawa
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Patent number: 4185291Abstract: A junction-type FET comprising a semiconductor substrate 21 of a first conductivity type, and island region 22 of a second conductivity type which comprises a channel region and is selectively formed in the semiconductor substrate 21, and a buried isolating region 27 which is selected from the group consisting of an intrinsic layer, a low impurity concentration layer of the second conductivity type and a layer of first conductivity type, the buried isolating layer being formed by ion implantation of impurities of the first conductivity type in the island region 22 while keeping the impurity concentration at the surface thereof relatively high, and the buried isolating layer substantially isolating the channel region from the surface.Type: GrantFiled: June 16, 1978Date of Patent: January 22, 1980Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Hirao, Shigetoshi Takayanagi, Takeshi Onuma, Toshio Sugawa, Kaoru Inoue