Patents by Inventor Toshio Tokita
Toshio Tokita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7864950Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: GrantFiled: March 8, 2001Date of Patent: January 4, 2011Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone CorporationInventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Patent number: 7822196Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: GrantFiled: October 28, 2005Date of Patent: October 26, 2010Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone CorporationInventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Patent number: 7760870Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: GrantFiled: October 28, 2005Date of Patent: July 20, 2010Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone CorporationInventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Patent number: 7760871Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: GrantFiled: October 28, 2005Date of Patent: July 20, 2010Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone CorporationInventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Patent number: 7697684Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: GrantFiled: October 28, 2005Date of Patent: April 13, 2010Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone CorporationInventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Patent number: 7184549Abstract: To encrypt another piece of data during encrypting process of a certain piece of data, a memory 55 is provided in parallel with a feedback line 65 which feeds back data from an encrypting module 51using an encryption key K to a selector 54. When an interrupt IT for processing plaintext block data N1 is generated while plaintext block data M1 is processed, ciphertext block data C1 at timing of generation of the interrupt IT is made to be stored in a register 56. The ciphertext block data C1 stored in the memory 55 is made to be selected by the selector 54 at timing of completion of processing the plaintext block data N1, and processing the plaintext block data M1+1 is started.Type: GrantFiled: December 22, 2000Date of Patent: February 27, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toru Sorimachi, Toshio Tokita
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Patent number: 7096369Abstract: In a data transformation apparatus for transforming two arbitrary pieces of data of A input data and B input data, a first nonlinear transformation of the A input data is performed using a first key parameter, a transformed result is output, an XOR operation of the transformed result and the B input data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. On the other hand, the B input data is input to a next sub-transformation unit as A input data. A second nonlinear transformation of the B input data is performed using a second key parameter, the transformed result is output, an XOR operation of the transformed result and the B intermediate data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data.Type: GrantFiled: May 22, 2002Date of Patent: August 22, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Matsui, Toshio Tokita
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Publication number: 20060050872Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: ApplicationFiled: October 28, 2005Publication date: March 9, 2006Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Publication number: 20060050874Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit ((FL?1)) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit ((FL?1)) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: ApplicationFiled: October 28, 2005Publication date: March 9, 2006Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Publication number: 20060050873Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: ApplicationFiled: October 28, 2005Publication date: March 9, 2006Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Publication number: 20060045265Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: ApplicationFiled: October 28, 2005Publication date: March 2, 2006Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Publication number: 20020181709Abstract: To encrypt another piece of data during encrypting process of a certain piece of data, a memory 55 is provided in parallel with a feedback line 65 which feeds back data from an encrypting module 51using an encryption key K to a selector 54. When an interrupt IT for processing plaintext block data Ni is generated while plaintext block data Mi is processed, ciphertext block data Ci at timing of generation of the interrupt IT is made to be stored in a register 56. The ciphertext block data Ci stored in the memory 55 is made to be selected by the selector 54 at timing of completion of processing the plaintext block data Ni, and processing the plaintext block data Mi+1 is started.Type: ApplicationFiled: December 6, 2001Publication date: December 5, 2002Inventors: Toru Sorimachi, Toshio Tokita
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Publication number: 20020159599Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL−1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL−1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.Type: ApplicationFiled: January 8, 2002Publication date: October 31, 2002Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
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Patent number: 6466669Abstract: The present invention can be applied to a cipher processing apparatus, which includes a function F having a configuration of repeating process and inside of the function F, a function f having a configuration of repeating process is included. According to the invention, the cipher processing apparatus is configured by registers 301 through 303 for temporarily holding data, selectors A through C, 311 through 313, and a function f operating circuit 323 for transforming data. An output data from the function f operating circuit 323 is held in the register C 303, and the selector C 313 selects either to repeat the data transformation by the function operating circuit 323 or not. When a cipher processing apparatus includes a function F having a configuration of repeating process and inside of the function F, a function f having a configuration of repeating process is included, the cipher processing apparatus can be embodied efficiently, which enables to reduce the circuit scale and to save electric power.Type: GrantFiled: December 31, 1998Date of Patent: October 15, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Matsui, Toshio Tokita
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Publication number: 20020131589Abstract: In a data transformation apparatus for transforming two arbitrary pieces of data of A input data and B input data, a first nonlinear transformation of the A input data is performed using a first key parameter, a transformed result is output, an XOR operation of the transformed result and the B input data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. On the other hand, the B input data is input to a next sub-transformation unit as A input data. A second nonlinear transformation of the B input data is performed using a second key parameter, the transformed result is output, an XOR operation of the transformed result and the B intermediate data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data.Type: ApplicationFiled: May 22, 2002Publication date: September 19, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Matsui, Toshio Tokita
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Patent number: 6415030Abstract: In a data transformation apparatus for transforming two arbitrary pieces of data of A input data and B input data, a first nonlinear transformation of the A input data is performed using a first key parameter, a transformed result is output, an XOR operation of the transformed result and the B input data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. On the other hand, the B input data is input to a next sub-transformation unit as A input data. A second nonlinear transformation of the B input data is performed using a second key parameter, the transformed result is output, an XOR operation of the transformed result and the B intermediate data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data.Type: GrantFiled: December 13, 2000Date of Patent: July 2, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Matsui, Toshio Tokita
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Publication number: 20010000708Abstract: In a data transformation apparatus for transforming two arbitrary pieces of data of A input data (101) and B input data (102), a first nonlinear transformation of the A input data is performed using a first key parameter (111), a transformed result (109) is output, an XOR operation of the transformed result and the B input data (102) is performed to output an XORed result as B intermediate data (106), and the B intermediate data is input to a next sub-transformation unit (122) as B input data. On the other hand, the B input data (102) is input to a next sub-transformation unit as A input data. A second nonlinear transformation of the B input data (102) is performed using a second key parameter (112), the transformed result is output, an XOR operation of the transformed result and the B intermediate data (106) is performed to output an XORed result as B intermediate data (108), and the B intermediate data is input to a next sub-transformation unit (123) as B input data.Type: ApplicationFiled: December 13, 2000Publication date: May 3, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Matsui, Toshio Tokita
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Patent number: 6201869Abstract: Data transformation apparatuses and methods for transforming two arbitrary pieces of data of A input data and B input data, wherein a first nonlinear transformation of the A input data is performed using a first key parameter, a transformed result is output, an XOR operation of the transformed result and the B input data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. On the other hand, the B input data is input to a next sub-transformation unit as A input data. A second nonlinear transformation of the B input data is performed using a second key parameter, the transformed result is output, an XOR operation of the transformed result and the B intermediate data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data.Type: GrantFiled: April 28, 1997Date of Patent: March 13, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Matsui, Toshio Tokita
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Patent number: 5912905Abstract: The present invention provides an error-correcting encoder and an error-correcting decoder which encode/decode a plurality of information symbols in parallel with a reduced number of shifts, which enables a reduction in the processing time. The error-correcting encoder of the invention includes a shift register including stages equal to a predetermined number of check symbols for inputting different information symbols in parallel from a plurality of input terminals. The encoder also includes a Galois field multiplier for multiplying each coefficient and a Galois field adder to obtain the predetermined number of check symbols from the information symbols. The encoder can generate the predetermined number of check symbols with shifts, the number of which is reduced according to the number of parallel inputs.Type: GrantFiled: February 20, 1997Date of Patent: June 15, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuyuki Sakai, Hideo Yoshida, Toshio Tokita
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Patent number: 5699368Abstract: The present invention provides an error-correcting encoder and an error-correcting decoder which encode/decode a plurality of information symbols in parallel with a reduced number of shifts, which enables a reduction in the processing time. The error-correcting encoder of the invention includes a shift-register including stages equal to a predetermined number of check symbols for inputting different information symbols in parallel from a plurality of input terminals. The encoder also includes a Galois field multiplier for multiplying each coefficient and a Galois field adder to obtain the predetermined number of check symbols from the information symbols. The encoder can generate the predetermined number of check symbols with shifts, the number of which is reduced according to the number of parallel inputs.Type: GrantFiled: February 7, 1995Date of Patent: December 16, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuyuki Sakai, Hideo Yoshida, Toshio Tokita