Abstract: The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed.

Abstract: To provide a technique capable of achieving high integration of semiconductor devices. A standard cell is provided in an n-type well, and includes a p+-type diffusion layer and n+-type diffusion layer covered with a metal silicide film. The p+-type diffusion layer constitutes a source/drain of an MIS transistor, and the n+-type diffusion layer constitutes a tap. The p+-type diffusion layer is electrically coupled to a wiring layer via a contact, and the n+-type diffusion layer is electrically coupled to a wiring layer via a contact. Moreover, the p+-type diffusion layer is in contact with the n+-type diffusion layer. A power supply potential supplied to the source node of the MIS transistor is provided using two layers, i.e., the diffusion layer and the wiring layer.

Abstract: A honeycomb structure excellent in thermal dispersibility upon heating and being protected from damage due to thermal stress, and an efficient method for manufacturing the honeycomb structure. The structure is provided with porous partition walls, functioning as a filtration layer, through which exhaust gas flowing into the cells can flow out, and plugging portions. Additional plugging portions are further disposed in the open end portions to which the plugging portions are not disposed (unplugged open end portions) not so as to plug unplugged open end portions. Each cross-sectional shape of additional plugging portions in a direction perpendicular to the axial direction forms a predetermined pattern shape as a whole, and a barycenter of the pattern shape is located in almost the center of a cross section of a flow of the exhaust gas in a direction perpendicular to the axial direction.

Abstract: [Object] To provide a tape cutter device that allows a cutting blade to be disposed at a non-adhesion-surface side of an adhesive tape and that can easily form a fold, including a non-adhesion portion, at a cut end portion of the adhesive tape after a cutting operation.

Abstract: A honeycomb filter system comprising a first honeycomb filter disposed upstream: first filter having partition wall matrix of a mean pore diameter of 25 ?m or more and below 70 ?m and a porosity of 40% or more and below 70%, and carrying an oxidation catalyst containing at least one material selected from the group consisting of platinum (Pt), palladium, ceria, and alumina in at least a part of inner surfaces of pores of the matrix; and a second honeycomb filter disposed downstream; having a surface layer of a peak pore diameter of 0.3 ?m or more and below 20 ?m which is equivalent to or smaller than that of its matrix, and a porosity of 60% or more and below 95% which is higher than that of the matrix; and having the other specified relations.

Abstract: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

Abstract: A vehicle seat includes: a seat cushion; and a front end transfer member which supports a front end of the seat cushion movably in a front-rear direction of a vehicle; and a rear end transfer member which supports a rear end of the seat cushion movably in a front-rear direction of the vehicle; wherein the seat cushion is storable in a storage concave part provided in a vehicle floor further to a rear than the seat cushion, and the front end transfer member is provided on a vehicle floor adjacent to the front of the storage concave part, and the rear end transfer member is provided on a vehicle floor adjacent to a side of the storage concave part, or provided on a side interior surface of the storage concave part.

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract: A power source noise of a semiconductor device having a core cell configuring a logic circuit is reduced. Above the core cell configuring the logic circuit provided on a main surface of a semiconductor substrate are provided a first branch line for a first power source of the core cell, which is electrically connected to a first power source trunk line, and a second branch line for a second power source of the core cell, which is electrically connected to a second power source trunk line. The first and second branch lines are oppositely provided, thereby forming a capacitor between the first and second power sources.

Abstract: According to the present invention, there is provided a honeycomb catalytic structure comprising: a honeycomb structure comprising porous partition walls having a large number of pores, disposed so as to form a plurality of cells extending between the two end faces of the honeycomb structure and plugging portions disposed at either one end of each cell, and a catalyst layer containing a catalyst, supported at least on the inner surfaces of the pores of the honeycomb structure, wherein the mass of the catalyst layer per unit volume (1 cm3) of the honeycomb structure (g/cm3) is 60% or less of the volume of pores per unit volume (1 cm3) of the honeycomb structure (cm3/cm3).

Abstract: A vehicle seat includes: a seat cushion; and a front end transfer member which supports a front end of the seat cushion movably in a front-rear direction of a vehicle; and a rear end transfer member which supports a rear end of the seat cushion movably in a front-rear direction of the vehicle; wherein the seat cushion is storable in a storage concave part provided in a vehicle floor further to a rear than the seat cushion, and the front end transfer member is provided on a vehicle floor adjacent to the front of the storage concave part, and the rear end transfer member is provided on a vehicle floor adjacent to a side of the storage concave part, or provided on a side interior surface of the storage concave part.

Abstract: This invention provides a honeycomb catalyst having an excellent purification efficiency and a small pressure loss and can be mounted even in a limited space, the honeycomb catalyst comprising: porous partition walls 4 having plural pores 25, which are arranged to form plural cells 3 allowing communication between two end faces; plugging portions being arranged to plug the cells 3 in one of the end faces; and catalytically active components 5, 15 loaded on surfaces of partition walls 4 and inner surfaces of pores 25, wherein many catalytically active component-loading pores 35 through which a gas can pass are formed in partition walls 4, and a ratio of a mass (MW) of the catalytically active component loaded on the surfaces of partition walls 4 to a mass (MP) of the catalytically active component 5 loaded on the inner surfaces of the pores 25 is (MW):(MP)=1:3 to 3:1.

Abstract: The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed.

Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract: The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed.

Abstract: A means suitable for producing and supplying exhaust gas for evaluation to be supplied to an exhaust gas purifying apparatus in a safe and stable manner and a means for correctly and accurately evaluating performance and durability of the exhaust gas purifying apparatus are provided. The PM generating apparatus 10 which can generate PM in a gas by combusting a liquid and/or gaseous fuel in the combustion chamber 2. The PM generating apparatus 10 is provided with a combustion chamber 1, a combustion air supply means 4 supplying combustion air to the combustion chamber 1, and an intermittent fuel injection means 3 which can intermittently inject the fuel to the combustion air supplied to the combustion chamber 1.

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract: An imaging method includes a step of setting, when a digital zoom operation mode for enlarging an image imaged by a imaging part of an X-Y address type is selected, a zoom magnification and enlarging the image at the zoom magnification set. The imaging method includes the steps of: setting an imaging range in a vertical direction of the imaging part according to the zoom magnification set in the digital zoom step; outputting a driving signal for scanning the shutter signal and the readout signal to perform exposure in the imaging range set in the imaging range setting step and driving the imaging part; and discarding, when the zoom magnification is changed in the digital zoom step, images imaged by the imaging part before and after the change of the zoom magnification to prevent the images from being used.

Abstract: A honeycomb catalyst body includes: porous partition walls having a large number of pores and disposed to form a plurality of cells communicating between two end faces, plugged portions disposed to plug each of the cells on one of the end faces, and catalyst layers loaded in layers on an inner surface of the cells and an inner surface of the pores and containing a noble metal. Mass (Mc) of the noble metal contained in the catalyst layer loaded on the inner surface of the cells and mass (Mp) of the noble metal contained in the catalyst layer loaded on the inner surface of the pores satisfy the relation of (Mp)/(Mc)?4. The honeycomb catalyst body is excellent in purification efficiency, has low pressure loss, and is mountable even in a limited space.