Patents by Inventor Toshio Yoshihara

Toshio Yoshihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11036668
    Abstract: An electronic apparatus includes a semiconductor integrated circuit, another semiconductor integrated circuit connected to the semiconductor integrated circuit via a peripheral component interconnect (PCI) bus, and devices (a hard disk drive (HDD), and a dynamic random access memory (DRAM)) connected to the another semiconductor integrated circuit. The semiconductor integrated circuit transmits a predetermined instruction to the another semiconductor integrated circuit, and the another semiconductor integrated circuit shifts the PCI bus to a non-communicable state or a state communicable at low speed. Thereafter, the another semiconductor integrated circuit shifts the devices (the HDD and the DRAM) to a power saving state.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 15, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshio Yoshihara, Hiroaki Niitsuma
  • Patent number: 10860331
    Abstract: An information processing which reduces production costs. The information processing apparatus has a first semiconductor device, a second semiconductor device, a ROM that stores both a first boot program and a second boot program, and an interface for communicating with the ROM. In response to the first semiconductor device being reset, the first semiconductor device reads out the first boot program from the ROM via the interface. In response to the second semiconductor device being reset, the second semiconductor device reads out the second boot program from the ROM via the interface. While the first semiconductor device is reading out the first boot program from the ROM, an output from the second semiconductor device to the interface is controlled to have high impedance.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 8, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Niitsuma, Toshio Yoshihara
  • Publication number: 20200377748
    Abstract: An ink composition comprising one or two or more kinds of rare-earth complexes containing trivalent rare-earth ions and at least one organic ligand selected from a ?-diketone ligand, a carboxylic acid ligand, a phosphine oxide ligand and a nitrogen-containing aromatic heterocyclic ligand, wherein at least one selected from the following group A and at least one selected from the following group B are contained as the trivalent rare-earth ions contained in the one or two or more kinds of rare-earth complexes: Group A: Eu3+, Sm3+, Pr3+ and Ho3+; and Group B: Tb3+, Er3+, Tm3+, Dy3+, Yb3+, Nd3+, Ce3+ and Gd3+.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 3, 2020
    Inventors: Yuko Aoyama, Jun Sato, Fumiyasu Murakami, Masato Okada, Toshio Yoshihara, Yasuchika Hasegawa, Takayuki Nakanishi
  • Publication number: 20200354596
    Abstract: An ink composition comprising: a rare-earth complex containing one kind of trivalent rare-earth ion selected from the group consisting of Eu3+, Tb3+, Sm3+, Er3+, Pr3+, Ho3+, Tm3+ and Dy3+, and a specific phosphine oxide ligand coordinated to the rare-earth ion, and a light-emitting material different from the rare-earth complex, wherein an absolute value of a difference between a wavelength (?1) at which a light emission intensity of the rare-earth complex is maximum and a wavelength (?2) at which a light emission intensity of the light-emitting material is maximum, is 50 nm or more.
    Type: Application
    Filed: June 1, 2018
    Publication date: November 12, 2020
    Inventors: Yuko Aoyama, Jun Sato, Fumiyasu Murakami, Masato Okada, Toshio Yoshihara
  • Publication number: 20200250125
    Abstract: An electronic apparatus includes a semiconductor integrated circuit, another semiconductor integrated circuit connected to the semiconductor integrated circuit via a peripheral component interconnect (PCI) bus, and devices (a hard disk drive (HDD), and a dynamic random access memory (DRAM)) connected to the another semiconductor integrated circuit. The semiconductor integrated circuit transmits a predetermined instruction to the another semiconductor integrated circuit, and the another semiconductor integrated circuit shifts the PCI bus to a non-communicable state or a state communicable at low speed. Thereafter, the another semiconductor integrated circuit shifts the devices (the HDD and the DRAM) to a power saving state.
    Type: Application
    Filed: January 28, 2020
    Publication date: August 6, 2020
    Inventors: Toshio Yoshihara, Hiroaki Niitsuma
  • Publication number: 20200073842
    Abstract: A bridge device according to an aspect of the present invention is configured to communicate with a first device and a second device, the first device being configured to interrupt output of a first clock signal after completion of the output of the data, the second device being controlled based on the data. The bridge device includes an acquisition unit configured to acquire the data based on the first clock signal, a storage unit configured to store the data acquired by the acquisition unit, and an output unit configured to read out the data stored in the storage unit and output the data to the second device. The output unit receives a second clock signal different from the first clock signal input from the first device, and outputs the data based on the second clock signal.
    Type: Application
    Filed: August 14, 2019
    Publication date: March 5, 2020
    Inventors: Yasushi Shinto, Toshio Yoshihara, Yasutomo Tanaka, Daisuke Matsunaga
  • Publication number: 20200076645
    Abstract: A bridge device connected to a master device and a plurality of memory devices, and includes a reception unit configured to receive a command for controlling a memory device, a memory address in the memory device, and data via a same signal line, the command, the memory address, and the data being output from the master device, an output unit configured to output the command received by the reception unit to at least one of the memory devices, and a selection unit configured to select a memory device to perform processing of the command received by the reception unit from among the plurality of memory devices based on the memory address received from the master device by the reception unit.
    Type: Application
    Filed: August 15, 2019
    Publication date: March 5, 2020
    Inventors: Yasutomo Tanaka, Daisuke Matsunaga, Toshio Yoshihara, Yasushi Shinto
  • Patent number: 10514870
    Abstract: An image forming apparatus which is capable of preventing degradation of operability associated with setting of job setting information. The image forming apparatus is unable to directly edit the job setting information required to execute a submitted job. The submitted job is executed based on the job setting information. In a case where user-specific setting information corresponding to identification information on a user who has logged into the image forming apparatus and corresponding to a type of the submitted job is registered in the image forming apparatus, the user-specific setting information is set as the job setting information.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 24, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Toshio Yoshihara, Yoshihisa Nomura, Masanori Ichikawa, Shigeki Hasui
  • Publication number: 20190332334
    Abstract: An image processing apparatus includes a wireless communication interface that wirelessly communicates with a mobile terminal, an element that initiates wireless communication with the mobile terminal, a light emitting element, associated with the element, that emits light, and at least one controller that causes the light emitting element to emit light in response to occurrence of an event requiring communication with the mobile terminal.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 31, 2019
    Inventors: Toshio Yoshihara, Yoshihisa Nomura, Shigeki Hasui, Masanori Ichikawa
  • Patent number: 10429916
    Abstract: A control apparatus that controls a memory, where the memory is capable of being shifted in accordance with a control signal to a power saving state. According to one embodiment, the control apparatus shifts the memory to the power saving state using the control signal on a basis of stopping of a clock signal input to the memory.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 1, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshio Yoshihara
  • Patent number: 10248432
    Abstract: An information processing apparatus according to an exemplary embodiment of the present invention includes a main system and a subsystem. The main system includes a first control unit configured to, before the information processing apparatus shifts to a power-saving state, develop a boot image to be executed by the subsystem in a memory of the subsystem. The subsystem includes a second control unit configured to, in a case where the information processing apparatus returns from the power-saving state, issue an instruction to execute the boot image developed in the memory. The subsystem further includes a third control unit configured to execute the boot image developed in the memory according to the instruction issued by the second control unit.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 2, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshio Yoshihara
  • Publication number: 20190095141
    Abstract: An image forming apparatus which is capable of preventing degradation of operability associated with setting of job setting information. The image forming apparatus is unable to directly edit the job setting information required to execute a submitted job. The submitted job is executed based on the job setting information. In a case where user-specific setting information corresponding to identification information on a user who has logged into the image forming apparatus and corresponding to a type of the submitted job is registered in the image forming apparatus, the user-specific setting information is set as the job setting information.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 28, 2019
    Inventors: Toshio Yoshihara, Yoshihisa Nomura, Masanori Ichikawa, Shigeki Hasui
  • Patent number: 10131809
    Abstract: The present invention provides an optical layered body having excellent antistatic properties, optical characteristics, hardness, adhesion, and interference fringe prevention performance, which can be produced at a low cost. An optical layered body having a hard coat layer provided on a triacetylcellulose substrate, wherein a resin composition used for forming the hard coat layer contains a quaternary ammonium salt-containing polymer, a binder resin, and a solvent; the quaternary ammonium salt-containing polymer has a higher hydrophilicity than the binder resin; and the binder resin contains two or more resin components having different hydrophilicities.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: November 20, 2018
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshio Yoshihara, Tomoyuki Horio, Mayu Youki
  • Publication number: 20180060081
    Abstract: An information processing which reduces production costs. The information processing apparatus has a first semiconductor device, a second semiconductor device, a ROM that stores both a first boot program and a second boot program, and an interface for communicating with the ROM. In response to the first semiconductor device being reset, the first semiconductor device reads out the first boot program from the ROM via the interface. In response to the second semiconductor device being reset, the second semiconductor device reads out the second boot program from the ROM via the interface. While the first semiconductor device is reading out the first boot program from the ROM, an output from the second semiconductor device to the interface is controlled to have high impedance.
    Type: Application
    Filed: August 18, 2017
    Publication date: March 1, 2018
    Inventors: Hiroaki Niitsuma, Toshio Yoshihara
  • Patent number: 9683108
    Abstract: There is provided an antireflective laminate having a low refractive index and excellent mechanical strength, which comprises a coating layer of an ionizing radiation curing-type resin composition comprising ionizing radiation curing group-containing hollow silica fine particles. The antireflective laminate comprises a light transparent base material and at least a low refractive index layer having a refractive index of not more than 1.45 provided on the light transparent base material, wherein the low refractive index layer comprises an ionizing radiation curing-type resin composition and silica fine particles having an outer shell layer with the interior of the silica fine particles being porous or void, and, for a part or all of the silica fine particles, at least a part of the surface of the silica fine particle has been treated with an ionizing radiation curing group-containing silane coupling agent.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 20, 2017
    Assignees: Dai Nippon Printing Co., Ltd., JGC Catalysts and Chemicals Ltd.
    Inventors: Utako Mizuno, Midori Nakajo, Seiji Shinohara, Toshio Yoshihara, Hiroyasu Nishida, Ryo Muraguchi, Masafumi Hirai
  • Publication number: 20170123473
    Abstract: A control apparatus that controls a memory, where the memory is capable of being shifted in accordance with a control signal to a power saving state. According to one embodiment, the control apparatus shifts the memory to the power saving state using the control signal on a basis of stopping of a clock signal input to the memory.
    Type: Application
    Filed: October 25, 2016
    Publication date: May 4, 2017
    Inventor: Toshio Yoshihara
  • Patent number: 9570642
    Abstract: Provided is a sealing material sheet for solar cell modules, which is obtained by irradiating a polyethylene resin with ionizing radiation and has high transparency, heat resistance and adhesion at the same time. This sealing material sheet for solar cell modules contains a low density polyethylene having a density of 0.900 g/cm3 or less, while having a gel fraction of from 0% to 40% (inclusive) and a degree of dispersity (Mw/Mn), which is the ratio of the weight average molecular weight (Mw) to the number average molecular weight (Mn) in terms of polystyrene, of from 2.5 to 3.5 (inclusive).
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: February 14, 2017
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Hideki Matsui, Kosuke Saeki, Yasushi Shirahige, Noritoshi Akazawa, Toshio Yoshihara
  • Patent number: 9489159
    Abstract: A method executed by an apparatus includes receiving selection of a function, and determining whether to perform hardware processing or software processing on the function based on a free space in a storage unit configured to store hardware information relating to the hardware processing on the function and function information relating to the function.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 8, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Toshio Yoshihara
  • Publication number: 20160295058
    Abstract: A flexible flat cable includes a first flat cable part having an electromagnetic shielding structure and flexibility, and a second flat cable part having an electromagnetic shielding structure and flexibility. The second flat cable part is different from the first flat cable part in at least one of electromagnetic shielding structure and flexibility.
    Type: Application
    Filed: July 31, 2015
    Publication date: October 6, 2016
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Toshio YOSHIHARA
  • Patent number: 9395807
    Abstract: A sleep mode in which power consumption is reduced to a prescribed value or smaller is achieved, while convenience for a user is maintained by shortening the time taken to recover from the sleep mode. The temperature of an LSI is measured or estimated when shifting to the sleep mode, and an apparatus enters a power supply shutoff sleep mode using power supply separation or a clock-gating sleep mode in accordance with the measured or estimated value of the temperature. In the case where power supply shutoff is selected, after entering the sleep mode, power supply is resumed and then the apparatus enters the clock-gating sleep mode in accordance with the measured temperature or the estimated temperature of the LSI.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: July 19, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Toshio Yoshihara