Abstract: A lateral bipolar CMOS integrated circuit having an inverter circuit including an n-channel MOS transistor and a p-channel MOS transistor, and having four terminals of: a gate input terminal Vin connected with the gates of the n-channel MOS transistor and the p-channel MOS transistor; an output terminal Vout connected with the drains of the n-channel MOS transistor and the p-channel MOS transistor; a p-type base terminal connected with a p-type substrate of the n-channel MOS transistor; and an n-type base terminal connected with an n-type substrate of the p-channel MOS transistor. The n-channel MOS transistor operates in a hybrid mode which is the hybrid of an operation mode of the MOS transistor and that of an npn lateral bipolar transistor which is inherent in the n-channel MOS transistor. The p-channel MOS transistor operates in a hybrid mode which is the hybrid of an operation mode of the MOS transistor and that of a pnp lateral bipolar transistor which is inherent in the p-channel MOS transistor.

Abstract: The invention provides a functional module model for realizing optimal pipelining. The functional module model includes division line data representing division lines corresponding to positions where pipeline registers can be inserted and delay/area data representing the trade-off relationship between the delay and the area of each division area partitioned by the division lines. By using this functional module model, a pipeline register insertion position is selected among the division lines represented by the division line data, and the delay and the area of each division area are set on the basis of the trade-off relationship represented by the delay/area data. Thus, a pipelined circuit with a minimized area can be synthesized.

Abstract: An initial placement is performed based on a net list and a cell library. An optimum effective temperature Tc is derived based on a cost value obtained if the positions of two components, selected from a list of exchange candidates (where all the components are registered), are exchanged with each other and a cost value before the exchange is performed. A first component and a second component, adjacent to the first component, are selected from the list of exchange candidates and the positions thereof are exchanged with each other. And at the optimum effective temperature Tc, it is determined in accordance with a Monte-Carlo method using the cost values before and after the exchange whether or not the exchange is allowable. If it is allowable, the placement after the exchange is decided as a new placement. Otherwise, the placement before the exchange is decided as a new placement.

Abstract: To reduce a circuit block in area, the present invention provides an LSI layout design method having a cell changing processing for reducing a pure wiring zone in area.By an input processing, circuit design information and cell library are entered. Then, a layout of cells arranged in a plurality of cell rows is designed by a cell placing processing. Then, the height of a wiring zone required between cell rows is estimated by a wiring zone height estimating processing. To reduce the area of a pure wiring zone other than the over-the-cell wiring zones, each of placed cells is changed, by a cell changing processing, to a cell having the same specifications and a different shape or a different terminal position. A layout of cell interconnection is designed by a wiring processing. Based on the layout thus obtained by the processings above-mentioned, a mask pattern is prepared and supplied by a mask pattern preparing processing.

Abstract: A drain-source interconnection of a MOS transistor is represented by a parallel circuit formed of an electric current source and a resistor. The current of the electric current source, i, is represented by a polynomial of a difference (V.sub.GS -V.sub.T) where V.sub.GS is the gate-source voltage and V.sub.T is the threshold voltage. The operation area of the MOS transistor is divided into a plurality of sub-operation areas according to the gate-source and drain-source voltages. Respective coefficients of the polynomial and respective conductance of the resistor element are stored for the sub-operation areas. A MOS transistor model is prepared so that V.sub.T is represented by a polynomial of V.sub.BS, the substrate-source voltage of the MOS transistor. A circuit equation for a MOS transistor-containing semiconductor circuit is derived from the MOS transistor model. The circuit equation is analyzed.

Abstract: A characteristic of a MOS transistor is represented using an equivalent model. The equivalent model shows a connection configuration made up of an electric current source which supplies an electric current and a resistor element which is connected in parallel with the electric current source. The electric current is given by the equation of i=G.sub.m .multidot.(V.sub.GS -V.sub.T) for V.sub.GS .gtoreq.V.sub.T where G.sub.m is a coefficient, V.sub.GS is a gate-to-source input voltage of said MOS transistor, and V.sub.T is a given threshold voltage. A plurality of operating zones of the MOS transistor are defined according to the drain, source, and gate terminal voltages of the MOS transistor and are assigned respective values of the coefficient G.sub.m and respective values of the resistor element's resistance. By such a representation, the circuit equation of a semiconductor circuit that is analyzed can be represented in the form of a linear time-invariant equation.

Abstract: A gate wire is formed so as to extend from an active area to a separation, and an impurity diffused area is formed on each side of the gate electrode located on the active area. A contact member for connecting the gate wire to a first layer aluminum interconnection formed in an upper layer of the gate wire is in contact with the gate wire at a portion located on the active area. The utilization ratio of the active area is thus improved, and hence, the width of the separation can be minimized. In addition, by eliminating a mask alignment margin from the gate wire and suppressing the width of the gate wire not to exceed the width of the contact member, the occupied area of a semiconductor apparatus can be reduced.

Abstract: The logic elements and net list contained in a logic circuit are inputted to an electronic calculator. The total number N1 of primary adjacent logic circuits which are connected directly to all the logic elements contained in the foregoing logic circuit, respectively is calculated from the inputted logic elements and net list. The total number N2 of primary and secondary adjacent logic circuits, which is the sum of the foregoing total number N1 of primary adjacent logic circuits and the total number of secondary adjacent logic circuits which are connected directly to the primary adjacent logic circuits, respectively, is calculated from the inputted logic elements and net list. The difference between the logarithmic value of the foregoing total number N1 of primary adjacent logic circuits and the logarithmic value of the foregoing total number N2 of primary and secondary adjacent logic circuits is calculated as a value for classification which characterizes the aforesaid logic circuit.

Abstract: A prophylactic and remedial preparation for a disease attendant on hyperglycemia, a preparation for depressing the rise in blood sugar, and a wholesome food separately include, as an active ingredient, at least one component selected from the group consisting of L-arabinose, L-fucose, 2-deoxy-D-galactose, D-xylose, L-xylose, D-ribose, D-tagatose, D-ribulose, D-lyxose and D-xylulose.

Abstract: A method for layout compaction which comprises steps of establishing storage areas in a direct access memory as a boundary information memory to which geometrical information on boundaries of a layout is written, searching layout elements of groups adjoining the boundaries of the layout and performing a processing of packing layout elements in a bottom boundary region of the layout and of packing layout elements in a top boundary region of the layout by using the boundary information memory. Thereby, a compaction of the layout can be performed at a high speed.

Abstract: There is provided a placement optimization system for determining layout in printed circuits and semiconductor substrates, comprising input means for inputting circuit connection information, placement optimization means for deriving wiring density distribution on the basis of the circuit connection information, evaluating the height and/or width of the wiring region statistically estimated from the wiring density distribution, and output means for outputting the resultant placement position information. Further, the placement optimization system may comprise means for collecting placement elements into sets, determining placement of the sets, then developing the sets into elements, and determining optimum placement positions of the elements.

Abstract: During an optimization of an organization of mutually-related elements, an element organization is gradually changed toward an objective specification by local changes of the element organization. A value of an objective function depends on a degree of a nearness of the element organization to the objective specification. A redundancy function of a number of elements in an improvement group is determined in consideration of a fluctuation in the value of the objective function, so that suitable changes of the improvement group are performed by use of the definite redundancy. An intermediate element organization is rejected and accepted in accordance with the redundancy function value, so that a final element organization can be obtained in consideration of a global aspect of the element organization.