Patents by Inventor Toshiro Sakamoto
Toshiro Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200309691Abstract: An optical density measuring apparatus for measuring density of a gas or a liquid to be measured includes a light source capable of irradiating light into a core layer, a detector capable of receiving light propagated through the core layer, and an optical waveguide that includes a substrate and the core layer. The core layer includes a light propagation unit and a first diffraction grating unit that receives light from the light source and guides the light to the light propagation unit, which includes a propagation channel capable of propagating light in an extending direction of the light propagation unit. The first diffraction grating unit is disposed near to and facing a light-emitting surface of the light source. The first diffraction grating unit includes first diffraction gratings, at least two of which receive light emitted from the same light-emitting surface of the light source.Type: ApplicationFiled: March 23, 2020Publication date: October 1, 2020Applicant: Asahi Kasei Microdevices CorporationInventors: Toshiro Sakamoto, Takaaki Furuya
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Publication number: 20200295197Abstract: There is provided a nonvolatile storage element having excellent charge holding characteristics capable of reducing variations in electric characteristics and an analog circuit provided with the same. A nonvolatile storage element is provided with a charge holding region and an insulator surrounding the entire surface of the charge holding region and having halogen distributed in at least one part of a region surrounding the entire surface.Type: ApplicationFiled: October 3, 2017Publication date: September 17, 2020Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventors: Toshiro SAKAMOTO, Satoshi TAKEHARA, Yoshiro YAMAHA, Makoto KOBAYASHI
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Publication number: 20200158635Abstract: An optical waveguide (10) includes a substrate (15), a core layer (11) that extends along the longitudinal direction and through which infrared light IR can propagate, and a support (17) formed from a material with a smaller refractive index than the core layer (11) and configured to connect at least a portion of the substrate (15) and at least a portion of the core layer (11) to support the core layer with respect to the substrate (15). A connecting portion (171) of the support (17) connected to the core layer (11) is shifted from the position having the shortest distance from the center to the outer surface in a cross-section perpendicular to the longitudinal direction of the core layer (11).Type: ApplicationFiled: February 19, 2018Publication date: May 21, 2020Applicant: Asahi Kasei Microdevices CorporationInventors: Toshiro SAKAMOTO, Tatsushi YAGI
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Publication number: 20200152618Abstract: This invention aims at providing a temperature characteristic adjustment circuit capable of adjusting the temperature characteristic to various positive and negative temperature characteristics with an excessively small characteristic variation and capable of suppressing an increase in the chip area and the current consumption with a simple circuit configuration. A temperature characteristic adjustment circuit has a current source having a nonvolatile storage element having a control gate region and a source region and driven by the application of a bias between the control gate region and the source region and an output circuit not having a nonvolatile storage element, in which the temperature dependency of an output signal originating from the temperature dependency of the current amount of a current output from the current source is adjusted by the nonvolatile storage element.Type: ApplicationFiled: October 3, 2017Publication date: May 14, 2020Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventors: Toshiro Sakamoto, Yuukou Tsushima
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Publication number: 20200116631Abstract: It is an object of this invention to provide an optical waveguide, an optical concentration measuring device, and a method for manufacturing an optical waveguide capable of achieving an improvement of evanescent wave exuding efficiency of propagating light and light extraction efficiency. A core layer provided in an optical waveguide has a first portion having a first film thickness, a second portion having a second film thickness different from the first film thickness, and a third portion connecting the first portion and the second portion. The third portion is formed so that the film thickness is gradually increased from the second portion having the smaller film thickness toward the first portion having the larger film thickness between the first portion and the second portion, and the maximum inclination angle is 10° or more and 45° or less.Type: ApplicationFiled: January 25, 2018Publication date: April 16, 2020Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventors: Toshiro SAKAMOTO, Takaaki FURUYA
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Publication number: 20200072748Abstract: Sticking of core layer is suppressed, and deterioration of sensitivity of a sensor is prevented. An optical waveguide (10) includes a substrate (15), a core layer (11), a support, and a protrusion (18). The core layer (11) can transmit light. The support connects at least a portion of the substrate (15) and a portion of the core layer (11) together. The support supports the core layer (11). The protrusion (18) is arranged at a position different from a position of the support in a space between the substrate (15) and the core layer (11). The protrusion (18) has a maximum height at a position deviated from a central position cp of the core layer (11) in a width direction. The protrusion (18) protrudes toward the core layer (11) from the substrate (15).Type: ApplicationFiled: August 30, 2019Publication date: March 5, 2020Applicant: Asahi Kasei Microdevices CorporationInventors: Tatsushi YAGI, Takaaki FURUYA, Toshiro SAKAMOTO
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Patent number: 10446567Abstract: To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a MOS transistor including a floating gate, a MOS transistor including a floating gate, and a MOS transistor including a floating gate.Type: GrantFiled: March 19, 2018Date of Patent: October 15, 2019Assignee: Asahi Kasei Microdevices CorporationInventors: Toshiro Sakamoto, Satoshi Takehara
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Publication number: 20190252998Abstract: A rectifying device 100 includes: at least one MOSFET (PMOSFET 20) having a gate terminal 26a, a drain terminal 25a, and a well terminal 23a that are interconnected; an AC signal generation source 80 that generates an AC signal to cause the at least one MOSFET to operate in a voltage region including a weak inversion region, and supplies the AC signal to a source terminal 24a of the MOSFET; and a capacitative element C connected to the drain terminal 25a of the MOSFET. As a rectifying element, a MOSFET that is driven even in a weak inversion region by short-circuiting the gate, drain, and well, and so have low rectification loss, and small leakage current is used; therefore, rectifying devices that are highly efficient, have low leakage current, can cope with high frequency, and thus are suitable for energy harvesting technologies to collect very weak energy are constituted.Type: ApplicationFiled: April 25, 2019Publication date: August 15, 2019Inventors: Toshiro SAKAMOTO, Masahiro MORIZUMI
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Publication number: 20190243405Abstract: The object of the present invention is to provide a current source which is capable of suppressing an increase in circuit size and by which a highly accurate constant current extremely stable to manufacturing variations or temperature fluctuations can be obtained. A current source circuit is provided with a nonvolatile storage element having a control gate region and a source region and operating as a field-effect transistor, and is configured to output a current in a state where a bias is applied between the control gate region and the source region.Type: ApplicationFiled: October 3, 2017Publication date: August 8, 2019Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventors: Toshiro SAKAMOTO, Yuukou TSUSHIMA
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Publication number: 20180286880Abstract: To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a MOS transistor including a floating gate, a MOS transistor including a floating gate, and a MOS transistor including a floating gate.Type: ApplicationFiled: March 19, 2018Publication date: October 4, 2018Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventors: Toshiro SAKAMOTO, Satoshi TAKEHARA
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Patent number: 9343554Abstract: A semiconductor device including a bipolar transistor in which a polysilicon film is used for an emitter electrode. The bipolar transistor includes a collector region formed in an Si substrate, a base layer formed on the collector region, an emitter region formed in an upper part spaced apart from the collector region of the base layers, and a silicon oxide film formed on the base layer and covering a joint portion of the base layer and the emitter region. The density of fluorine existent at an interface between the joint portion and the silicon oxide film is equal to or higher than 1×1020 cm?3.Type: GrantFiled: February 24, 2014Date of Patent: May 17, 2016Assignee: Asahi Kasei Microdevices CorporationInventor: Toshiro Sakamoto
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Publication number: 20160005840Abstract: A semiconductor device including a bipolar transistor in which a polysilicon film is used for an emitter electrode. The bipolar transistor includes a collector region formed in an Si substrate, a base layer formed on the collector region, an emitter region formed in an upper part spaced apart from the collector region of the base layers, and a silicon oxide film formed on the base layer and covering a joint portion of the base layer and the emitter region. The density of fluorine existent at an interface between the joint portion and the silicon oxide film is equal to or higher than 1×1020 cm?3.Type: ApplicationFiled: February 24, 2014Publication date: January 7, 2016Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventor: Toshiro SAKAMOTO
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Patent number: 9048252Abstract: There are provided a semiconductor device having a drain region making a BLDD structure withstandable against a high voltage, sufficiently suppressing a hot-carrier deterioration, and having a high ESD withstandable characteristic, and a method for manufacturing the same. A semiconductor device is formed including a MOS transistor having a source region and a drain region both formed in a semiconductor substrate, and a channel region formed therebetween. At this time, the concentration of holes emitted form P-type impurities injected into the channel region and contributing an electrical conduction is lower at a side close to the drain region than at a side close to the source region. The drain region includes a drift region into which N-type impurities are injected. The drift region extends toward the channel region from the drain region except a nearby area to the surface of the semiconductor substrate.Type: GrantFiled: March 9, 2012Date of Patent: June 2, 2015Assignee: Asahi Kasei Microdevices CorporationInventor: Toshiro Sakamoto
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Patent number: 9034709Abstract: A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate.Type: GrantFiled: February 20, 2013Date of Patent: May 19, 2015Assignee: Asahi Kasei Microdevices CorporationInventors: Shogo Katsuki, Toshiro Sakamoto
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Publication number: 20150024564Abstract: A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate.Type: ApplicationFiled: February 20, 2013Publication date: January 22, 2015Inventors: Shogo Katsuki, Toshiro Sakamoto
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Publication number: 20130341716Abstract: There are provided a semiconductor device having a drain region making a BLDD structure withstandable against a high voltage, sufficiently suppressing a hot-carrier deterioration, and having a high ESD withstandable characteristic, and a method for manufacturing the same. A semiconductor device is formed including a MOS transistor having a source region and a drain region both formed in a semiconductor substrate, and a channel region formed therebetween. At this time, the concentration of holes emitted form P-type impurities injected into the channel region and contributing an electrical conduction is lower at a side close to the drain region than at a side close to the source region. The drain region includes a drift region into which N-type impurities are injected. The drift region extends toward the channel region from the drain region except a nearby area to the surface of the semiconductor substrate.Type: ApplicationFiled: March 9, 2012Publication date: December 26, 2013Applicant: ASAHI KASEI MICRODEVICES CORPORATIONInventor: Toshiro Sakamoto