Patents by Inventor Toshitada Saito
Toshitada Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977940Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.Type: GrantFiled: July 7, 2021Date of Patent: May 7, 2024Assignee: Kioxia CorporationInventors: Akihisa Fujimoto, Toshitada Saito, Noriya Sakamoto, Atsushi Kondo
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Patent number: 11960320Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: GrantFiled: April 17, 2023Date of Patent: April 16, 2024Assignee: KIOXIA CORPORATIONInventors: Toshitada Saito, Akihisa Fujimoto
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Publication number: 20240015991Abstract: According to one embodiment, a memory device is disclosed. The memory device includes a substrate, an on-volatile memory, a memory controller, an interconnect including one end and another end. The one end is connected to the memory controller. A footprint is on the substrate and connected to the another end of the interconnect. An ESD protection element is on the substrate and connected to the footprint. A connection terminal is on the substrate and connectable to a host device. A via plug is in the substrate. One end of the via plug is connected to the another end of the interconnect and another end of the first plug is connected to the connection terminal.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Applicant: Kioxia CorporationInventors: Toshitada SAITO, Yasuo OTSUKA, Atsushi KONDO
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Publication number: 20230376440Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Applicant: KIOXIA CORPORATIONInventors: Kunihiko YAMAGISHI, Toshitada SAITO
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Patent number: 11762800Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.Type: GrantFiled: October 13, 2021Date of Patent: September 19, 2023Assignee: Kioxia CorporationInventors: Kunihiko Yamagishi, Toshitada Saito
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Publication number: 20230251682Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Applicant: KIOXIA CORPORATIONInventors: Toshitada SAITO, Akihisa FUJIMOTO
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Patent number: 11656651Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: GrantFiled: August 11, 2022Date of Patent: May 23, 2023Assignee: Kioxia CorporationInventors: Toshitada Saito, Akihisa Fujimoto
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Publication number: 20220382318Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: ApplicationFiled: August 11, 2022Publication date: December 1, 2022Applicant: Kioxia CorporationInventors: Toshitada SAITO, Akihisa FUJIMOTO
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Patent number: 11460878Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: GrantFiled: July 14, 2021Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventors: Toshitada Saito, Akihisa Fujimoto
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Publication number: 20220066973Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.Type: ApplicationFiled: October 13, 2021Publication date: March 3, 2022Applicant: Toshiba Memory CorporationInventors: Kunihiko YAMAGISHI, Toshitada SAITO
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Patent number: 11176079Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8 b/10 b coding for the symbol. The transmission unit transmits the symbol coded by the 8 b/10 b coding unit to the host apparatus.Type: GrantFiled: November 20, 2020Date of Patent: November 16, 2021Assignee: Toshiba Memory CorporationInventors: Kunihiko Yamagishi, Toshitada Saito
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Publication number: 20210341961Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Toshitada SAITO, Akihisa FUJIMOTO
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Publication number: 20210334617Abstract: According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.Type: ApplicationFiled: July 7, 2021Publication date: October 28, 2021Applicant: Kioxia CorporationInventors: Akihisa FUJIMOTO, Toshitada SAITO, Noriya SAKAMOTO, Atsushi KONDO
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Patent number: 11099597Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.Type: GrantFiled: April 19, 2019Date of Patent: August 24, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshitada Saito, Akihisa Fujimoto
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Patent number: 11093811Abstract: A memory card includes a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.Type: GrantFiled: March 9, 2018Date of Patent: August 17, 2021Assignee: Kioxia CorporationInventors: Akihisa Fujimoto, Toshitada Saito, Noriya Sakamoto, Atsushi Kondo
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Publication number: 20210073164Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8 b/10 b coding for the symbol. The transmission unit transmits the symbol coded by the 8 b/10 b coding unit to the host apparatus.Type: ApplicationFiled: November 20, 2020Publication date: March 11, 2021Applicant: Toshiba Memory CorporationInventors: Kunihiko YAMAGISHI, Toshitada SAITO
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Patent number: 10877917Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.Type: GrantFiled: October 4, 2019Date of Patent: December 29, 2020Assignee: Toshiba Memory CorporationInventors: Kunihiko Yamagishi, Toshitada Saito
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Patent number: 10714853Abstract: According to one embodiment, a semiconductor storage device includes a housing, a plurality of terminals, signal terminals, a controller, signal wiring, and a memory. The housing has a first face and a second face opposite to the first face. The plurality of terminals is exposed to the first face, extends in a first direction, and is spaced apart in a second direction intersecting with the first direction. A signal terminal included in the plurality of terminals has a first end in the first direction, and a second end opposite to the first end in the first direction, the second end being closer to a contact position with a socket contact than the first end. The controller is located in the housing. The signal wiring extends from the first end in the housing and electrically connects the first end and the controller. The memory is electrically connected to the controller in the housing.Type: GrantFiled: February 27, 2019Date of Patent: July 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshitada Saito, Hideki Kawamura, Atsushi Kondo, Katsuyoshi Watanabe, Taku Nishiyama
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Publication number: 20200090020Abstract: A memory card includes a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.Type: ApplicationFiled: March 9, 2018Publication date: March 19, 2020Applicant: Kioxia CorporationInventors: Akihisa FUJIMOTO, Toshitada SAITO, Noriya SAKAMOTO, Atsushi KONDO
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Publication number: 20200034324Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.Type: ApplicationFiled: October 4, 2019Publication date: January 30, 2020Applicant: Toshiba Memory CorporationInventors: Kunihiko YAMAGISHI, Toshitada Saito