Patents by Inventor Toshitaka Akahoshi
Toshitaka Akahoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10109660Abstract: A laminated semiconductor device includes: a first semiconductor element provided with a photoelectric conversion region on its main surface; an extended portion extended outwardly from a side end surface of the first semiconductor element; a redistribution layer formed on a first surface of the extended portion; a second semiconductor element provided on the main surface of the first semiconductor element so as to extend to the extended portion from an outside of the photoelectric conversion region, the second semiconductor element being electrically connected to the first semiconductor element and the redistribution layer; and a first electrode pad formed on the redistribution layer and electrically connected to the second semiconductor element via the redistribution layer.Type: GrantFiled: July 23, 2015Date of Patent: October 23, 2018Assignee: PANASONIC CORPORATIONInventors: Shigefumi Dohi, Toshitaka Akahoshi
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Patent number: 10090350Abstract: A light receiving device includes: a photoelectric converter including a photodiode and a first pixel electrode disposed on a lower surface of the photodiode; a scanning circuit connected to the first pixel electrode; an electrode pad disposed on a periphery of the scanning circuit; a transparent conductive film extending from an upper surface of the photodiode to the electrode pad, the transparent conductive film having an inclination relative to the upper surface of the photodiode, between the photodiode and the electrode pad; and a sealing resin filled in a space between the photoelectric converter and the scanning circuit, and in a space under the transparent conductive film around the photoelectric converter.Type: GrantFiled: October 13, 2016Date of Patent: October 2, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Masato Kobayashi, Manabu Usuda, Toshitaka Akahoshi
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Publication number: 20170033142Abstract: A light receiving device includes: a photoelectric converter including a photodiode and a first pixel electrode disposed on a lower surface of the photodiode; a scanning circuit connected to the first pixel electrode; an electrode pad disposed on a periphery of the scanning circuit; a transparent conductive film extending from an upper surface of the photodiode to the electrode pad, the transparent conductive film having an inclination relative to the upper surface of the photodiode, between the photodiode and the electrode pad; and a sealing resin filled in a space between the photoelectric converter and the scanning circuit, and in a space under the transparent conductive film around the photoelectric converter.Type: ApplicationFiled: October 13, 2016Publication date: February 2, 2017Inventors: Masato KOBAYASHI, Manabu USUDA, Toshitaka AKAHOSHI
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Patent number: 9502455Abstract: A downsized, highly reliable optical apparatus is stably and easily manufactured with high productivity. The optical apparatus includes: an optical device having a principal surface including an optical unit; a transparent member disposed facing the optical unit; a semiconductor device disposed above a back surface of the optical device and electrically connected to the optical device, the back surface being opposite the principal surface; and a resin member provided in a region adjacent to the optical device and the semiconductor device above a surface of the transparent member, the surface of the transparent member facing the optical device.Type: GrantFiled: May 26, 2015Date of Patent: November 22, 2016Assignee: PANASONIC CORPORATIONInventors: Toshitaka Akahoshi, Hiroki Yamashita, Shigefumi Dohi
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Publication number: 20150333096Abstract: A laminated semiconductor device includes: a first semiconductor element provided with a photoelectric conversion region on its main surface; an extended portion extended outwardly from a side end surface of the first semiconductor element; a redistribution layer formed on a first surface of the extended portion; a second semiconductor element provided on the main surface of the first semiconductor element so as to extend to the extended portion from an outside of the photoelectric conversion region, the second semiconductor element being electrically connected to the first semiconductor element and the redistribution layer; and a first electrode pad formed on the redistribution layer and electrically connected to the second semiconductor element via the redistribution layer.Type: ApplicationFiled: July 23, 2015Publication date: November 19, 2015Inventors: SHIGEFUMI DOHI, TOSHITAKA AKAHOSHI
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Publication number: 20150255500Abstract: A downsized, highly reliable optical apparatus is stably and easily manufactured with high productivity. The optical apparatus includes: an optical device having a principal surface including an optical unit; a transparent member disposed facing the optical unit; a semiconductor device disposed above a back surface of the optical device and electrically connected to the optical device, the back surface being opposite the principal surface; and a resin member provided in a region adjacent to the optical device and the semiconductor device above a surface of the transparent member, the surface of the transparent member facing the optical device.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Inventors: TOSHITAKA AKAHOSHI, HIROKI YAMASHITA, SHIGEFUMI DOHI
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Publication number: 20100127382Abstract: A semiconductor device includes: a semiconductor carrier with a top surface on which a plurality of electrodes are disposed; and a semiconductor element electrically connected through a plurality of bump electrodes to the plurality of associated electrodes. The plurality of electrodes are substantially uniformly spaced.Type: ApplicationFiled: September 24, 2009Publication date: May 27, 2010Inventors: Toshitaka AKAHOSHI, Teppei IWASE, Yoshiaki TAKEOKA
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Publication number: 20100044880Abstract: A semiconductor device includes a multilayer wiring substrate having a plurality of inner wiring layers and a semiconductor chip mounted on the multilayer wiring substrate. The multilayer wiring substrate has a groove formed in the bottom surface. The groove does not reach the lowermost of the inner wiring layers.Type: ApplicationFiled: April 22, 2009Publication date: February 25, 2010Inventors: Isamu AOKURA, Takashi YUI, Toshitaka AKAHOSHI
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Patent number: 7521288Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.Type: GrantFiled: March 14, 2007Date of Patent: April 21, 2009Assignee: Panasonic CorporationInventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
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Publication number: 20090091039Abstract: According to the present invention, for collective molding of semiconductor devices, a semiconductor substrate includes first electrodes formed on the front side, second electrodes formed on the back side and connected to external electrode terminals, and a plurality of semiconductor element mounting regions 203. Along partition lines 202 for partitioning the semiconductor substrate into the plurality of semiconductor element mounting regions 203, recessed portions 205 are formed on the partition lines 202 on the front side of the semiconductor substrate.Type: ApplicationFiled: June 12, 2008Publication date: April 9, 2009Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Toshitaka Akahoshi
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Patent number: 7298045Abstract: A first semiconductor element and second semiconductor element are bonded via die-bonding material. A first electrode of the first semiconductor element and a third electrode are joined, by means of flip-chip bonding, to a semiconductor carrier that has the third electrode on the one face of the semiconductor carrier and a fourth electrode on the perimeter of the other face of the semiconductor carrier. The bonding pad of the second semiconductor element and the fourth electrode of the semiconductor carrier are connected via fine metal wire by means of wire bonding. The periphery of the first semiconductor element and the wiring portion of the fine metal wire are filled with insulating sealing resin between the semiconductor carrier and second semiconductor element and the sealing fill region for the sealing resin is formed substantially the same as the external dimensions of the second semiconductor element.Type: GrantFiled: November 24, 2004Date of Patent: November 20, 2007Assignee: Matsushita Electric Industrial Co., LtdInventors: Hisaki Fujitani, Fumito Itou, Toshitaka Akahoshi, Toshiyuki Fukuda
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Publication number: 20070187811Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.Type: ApplicationFiled: March 14, 2007Publication date: August 16, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
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Patent number: 7239021Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.Type: GrantFiled: June 30, 2004Date of Patent: July 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
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Publication number: 20060220207Abstract: A metal pattern for heat dissipation is formed on the backside of a second semiconductor substrate, the metal pattern being in contact with a first semiconductor element mounted on a semiconductor device adjacent to the backside. Vias are formed on the peripheries of semiconductor substrates, the vias penetrating in the thickness direction to transmit heat. The vias and the metal pattern for heat dissipation are connected to each other on the backside of the semiconductor substrate. Solder balls disposed between the semiconductor devices transmit heat having been transmitted to the metal pattern of the semiconductor device to the vias of the semiconductor device adjacent to the backside of the semiconductor device having the metal pattern.Type: ApplicationFiled: March 16, 2006Publication date: October 5, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Toshitaka Akahoshi
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Publication number: 20060202793Abstract: A metal exposing portion (12) exposed from a surface of a base (2) between an internal terminal portion (8) and an external terminal portion (9) is formed in a metal wiring (7) embedded in the base (2). Accordingly, in a case where a solder ball is not mounted on the external terminal portion (9), although a bled component flows from sealing resin along the upper surface of the base (2) during a manufacturing method, the bled component stops by the metal exposing portion (12) which function as a breakwater and thus the bled component can be prevented from covering the external terminal portion (9).Type: ApplicationFiled: March 13, 2006Publication date: September 14, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Toshitaka Akahoshi
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Publication number: 20050116353Abstract: A first semiconductor element and second semiconductor element are bonded via die-bonding material. A first electrode of the first semiconductor element and a third electrode are joined, by means of flip-chip bonding, to a semiconductor carrier that has the third electrode on the one face of the semiconductor carrier and a fourth electrode on the perimeter of the other face of the semiconductor carrier. The bonding pad of the second semiconductor element and the fourth electrode of the semiconductor carrier are connected via fine metal wire by means of wire bonding. The periphery of the first semiconductor element and the wiring portion of the fine metal wire are filled with insulating sealing resin between the semiconductor carrier and second semiconductor element and the sealing fill region for the sealing resin is formed substantially the same as the external dimensions of the second semiconductor element.Type: ApplicationFiled: November 24, 2004Publication date: June 2, 2005Applicant: Matsushita Elec. Ind. Co. Ltd.Inventors: Hisaki Fujitani, Fumito Itou, Toshitaka Akahoshi, Toshiyuki Fukuda
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Publication number: 20050003580Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.Type: ApplicationFiled: June 30, 2004Publication date: January 6, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi