Abstract: In an electronic sphygmomanometer for a vehicle having a Korotkoff sound detecting circuit, a cuff pressure detecting circuit, a Korotkoff reference signal generator, a central processing unit for receiving the output of the Korotkoff sound detecting circuit, the output of the cuff pressure detecting circuit and the output of the Korotkoff reference signal generating and determining a systolic and diastolic blood pressure and a display unit for indicating the systolic and diastolic blood pressure, the electronic sphygmomanometer includes a cardioelectric potential detecting circuit having one-shot pulse generating circuit and the Korotkoff reference signal generator includes a flip-flop for receiving a cardioelectric potential synchronizing signal and pulse pressure variations signal so that the electronic sphygmomanometer mounted on the vehicle is not very much adversely affected by the vibration and noise.

Abstract: A semiconductor memory device includes a plurality of memory cells arranged in a matrix form and a decoder circuit selecting a row of the matrix in response to an address signal. The decoder circuit includes a first-stage decoder having a plurality of first-stage decoding elements and a second-stage decoder having a plurality of second-stage decoding elements. Each first-stage decoding element is connected to a plurality of second-stage decoding elements. Each of the first-stage decoding elements receives predetermined higher bits of the address signals. One of the first-stage decoding elements is selected upon one access command. Each of the plurality of second-stage decoding elements receives the address signals. One of the rows of the matrix is selected in response to the the address signals when the corresponding first-stage decoding element operates, whereby the power consumption is reduced.

Abstract: An electronic sphygmomanometer comprises a detection section formed with an analog circuit and includes a detection circuit for detecting Korotkoff sounds, a pressure transducer for converting a pressure to an electric signal, and an analog section of analog to digital converter on one bipolar IC chip, a logical section formed with a digital circuit and including a digital section of analog to digital converter, an arithmetic unit and a display device for indicating systolic and diastolic pressure on the other MOS IC chip, and a plurality of signal lines connected between the detection section and the logic section so that the sphygmomanometer is attained to be small and low voltage and current driver type.

Abstract: An output buffer circuit capable of three-output states of high and low levels and a high impedance. The output buffer circuit includes a detector circuit for detecting that a power source voltage for the buffer circuit is particularly high and for turning the output of the buffer circuit to the high impedance state when the high voltage is detected.

Abstract: When a side of a hole formed in a layer of a semiconductor device is located on a slope of a step-like portion, the side of the hole is formed so that it has a wave shape. A conductor line traverses the wave side of the hole.

Abstract: In semiconductor devices, the transistors are isolated by means of either a PN junction isolation method or a passive isolation (PI) method. The present invention aims to improve the PI method, which is disadvantageous in that an electrode, electrically connected to the semiconductor substrate, causes a decrease in the integration density of the IC chip. In the present invention, the vacant space outside the element-forming regions is used to form the electrode and the integration density is not decreased due to the formation of the electrode. Since a polycrystalline silicon layer is in a groove formed in the vacant space, ohmic contact between the polycrystalline semiconductor material in the layer and the semiconductor substrate can be achieved while at the same time keeping the diffusion length of the impurities diffused from the polycrystalline silicon layer and the semiconductor substrate, very short. Therefore, upward diffusion of the impurities from the N.sup.

Abstract: A semiconductor device includes therein a plurality of semiconductor elements. First passive isolation regions are formed along the buried layer and second passive isolation regions are formed perpendicularly along the buried layer, enclosing each of the semiconductor elements, additional passive isolation regions are provided at the end portions of the second passive isolation regions wherever the first and second passive isolation regions merge. The additional passive isolation regions are deeper than the second passive isolation regions.

Abstract: A field programmable device comprises regular word lines, regular bit lines, regular memory cells connected at the intersections of the regular word lines and the regular bit lines, at least one test word line adjacent to one of the regular bit lines, and alternately arranged conducting and nonconducting test memory cells arranged at the intersections of the test bit lines and the regular word lines. According to the invention, for the purpose of determining poor insulation between the word lines, the test bit line and the regular word line are insulated by an insulating layer in each nonconducting test memory cell.

Abstract: A field programmable device comprising a memory cell part and a plurality of test bit rows provided along bit lines of the memory cell part and/or a plurality of test word rows provided along word lines of the memory cell part. At least one of the rows of the test bit and/or test word rows is written-in with a write-in ratio different than those of the other test bit and/or test word rows.

Abstract: A semiconductor memory device which writes information by rendering particular memory cells conductive or non-conductive, wherein, when a selected memory cell is to be read out, a power supply voltage is applied to the collector of a transistor which feeds a base current to a final stage transistor of a decoder circuit which is connected to word lines, and when information is to be written in, a voltage higher than the power supply voltage is applied to the same collector.

Abstract: A PROM (programmable read-only memory) device includes both PROM cells and peripheral circuits cooperating therewith with the PROM cells and peripheral circuits formed in and on the same bulk. The bulk is formed free of metal which acts as a life time killer. Further, in each of the PROM cells, a buffer layer made of a silicon semiconductor, is introduced between a metal electrode, acting as a bit line, and the surface of the bulk at the position where the PROM cell is formed. Furthermore, the peripheral circuits are made by using Schottky TTL (transistor transistor logic) circuits.

Abstract: A PROM device having the improved bit address decoders composed of a plurality of AND gates, each of the AND gates comprising PNP type transistors, to each base of which is applied an address signal from the bit address inverters. Each collector of these transistors is connected to ground, and each emitter is connected to the output terminal of the bit address decoder.

Abstract: A three-state output circuit is disclosed. The three-state output circuit is comprised of a phase-splitter transistor, a pull-up transistor and a pull-down transistor and further comprised of a control circuit which operates to make the transistors active or non-active. At least one of said transistors is connected to the control circuit via a newly employed PNP transistor through its emitter and base. The collector thereof is connected to a ground point of the three-state output circuit.

Abstract: A field programmable device having a memory cell member including regular bit lines, regular word lines, regular memory cells connected at the cross points of said regular bit lines and regular word lines, test bit or test word lines, and non-conductive and conductive test memory cells connected at the cross points of said regular bit or regular word lines and test word or test bit lines, wherein the conductivity of a test memory cell is determined by the "1" or "0" of the address signal by which the test word or test bit line to which the test memory cell is connected is selected.

Abstract: A semiconductor integrated circuit comprising a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, which is of a conductivity type opposite to that of the substrate, a buried layer of a conductivity type opposite to that of the semiconductor substrate, lying between the semiconductor substrate and the epitaxial layer, a dielectric isolation region arranged apart from the buried layer and extending from a surface of the epitaxial layer to the semiconductor substrate, and elements formed in a portion of the epitaxial layer enclosed by the dielectric isolation region. The semiconductor integrated circuit is characterized in that an insulative leakage current blocking region is provided in the portion of the epitaxial layer enclosed by said region, in an arrangement enclosing at least a portion of the elements and extending from the surface of the epitaxial layer to the buried layer.

Abstract: A program circuit for permanently storing data into a programmable read only memory. A programming current (received from an external source) is connected to the selected bit line through a Darlington pair which is controlled by the bit decoding circuitry. Thus, the bit decoding circuitry is not required to pass the large programming current, and the programming current is not significantly shunted away from the selected bit line. To facilitate use of the Darlington configuration, a constant current source is provided for each bit line within a set of bit lines. The program circuit includes at least one switching means for connecting the program current to a selected bit line, a bit decoder connected to the control inputs of the switching means for selecting a bit line in response to the addressing signals input to the bit decoder and a control current supplying means for supplying a control current to the control inputs of the switching means.

Abstract: A screw-in station protector assembly includes a carrier housing containing a shorting cage which is biased by a compression to urge the cage and gas tube arrester assembly outwardly. The gas tube assembly contained within the cage includes a two electrode gas tube. The gas tube is within a jacket which forms a sealed external back-up air gap protector. The screw-in-assembly is particularly adapted for retro-fitting/replacement of carbon block arresters without modification.

Abstract: In a semiconductor memory device having a plurality of memory cells located at a cross position of a plurality of bit lines and a plurality of word lines, the memory cell comprising a series circuit of an information storing element such as a diode or a fuse and a PNP type transistor. An N type epitaxial layer is used as a word line and the P type semiconductor substrate is used as a collector output line.