Abstract: A power semiconductor chip (first semiconductor chip) 41 is mounted on the main surface of a first radiator plate 31, and a control IC chip (second semiconductor chip) 42 is mounted on the main surface of a second radiator plate 32. The first radiator plate 31 has an extending portion 31A extending toward the side on which the second radiator plate 32 is provided in the arrangement direction of first lead terminals (lead terminals 21 to 24). The first lead terminals (lead terminals 21 to 24) are connected to a first side of the first radiator plate 31 to function as extraction electrodes of a rear side electrode (D: drain electrode) of the power semiconductor chip 41. A second lead terminal (lead terminal 25) is connected to a bonding pad 411 serving as a source electrode (S). The third lead terminals (lead terminals 26 to 28) are connected to an electrode of the control IC chip 42.

Abstract: A power semiconductor chip (first semiconductor chip) 41 is mounted on the main surface of a first radiator plate 31, and a control IC chip (second semiconductor chip) 42 is mounted on the main surface of a second radiator plate 32. The first radiator plate 31 has an extending portion 31A extending toward the side on which the second radiator plate 32 is provided in the arrangement direction of first lead terminals (lead terminals 21 to 24). The first lead terminals (lead terminals 21 to 24) are connected to a first side of the first radiator plate 31 to function as extraction electrodes of a rear side electrode (D: drain electrode) of the power semiconductor chip 41. A second lead terminal (lead terminal 25) is connected to a bonding pad 411 serving as a source electrode (S). The third lead terminals (lead terminals 26 to 28) are connected to an electrode of the control IC chip 42.

Abstract: All lead terminals 21 to 24 formed on a first side of a first radiator plate 31 are set as terminals D which are connected to one of the main electrodes of a power semiconductor chip 11 through which a switching current flows. A lead terminal 25 formed on a second side of the first radiator plate 31 is set as a terminal S connected to the other one of the main electrodes of the power semiconductor chip 11. A lead terminal 28 formed on the second side of the first radiator plate 31 is set as a terminal FB to which a control signal of a control IC chip 12 is input. Lead terminals 26 and 27 formed between the lead terminals 25 and 28 are set as a terminal Vcc and a terminal GND, respectively.

Abstract: A power converter is provided which comprises two main MOS-FETs 4, 5 connected in series to a DC power source 1; an oscillator 2 which has two capacitors 3a, 3b connected in parallel to main MOS-FETs 4, 5; a primary winding 9a of a transformer 9 connected between a junction of two main MOS-FETs 4, 5 and a junction of two capacitors 3a, 3b; an electricity controller 12, 37 which comprises first and second regulatory MOS-FETs 10, 35, 12, 37 connected between respectively one and the other ends of a secondary winding 9b, 9c of transformer 9 and a speaker 15, 40; a polarity detector 51 for detecting the polarity of AC voltage produced on secondary winding 9b, 9c of transformer 9 by the on and off operation of MOS-FETs 4, 5 to generate detection signals; and a drive circuit 24, 25, 49, 50 for receiving detection signals from polarity detector 51 to control the on and off operation of first and second regulatory MOS-FETs 10, 35, 11, 36 to simplify the circuit configuration and improve power conversion efficiency in

Abstract: A power converter is provided which comprises two main MOS-FETs 4, 5 connected in series to a DC power source 1; an oscillator 2 which has two capacitors 3a, 3b connected in parallel to main MOS-FETs 4, 5; a primary winding 9a of a transformer 9 connected between a junction of two main MOS-FETs 4, 5 and a junction of two capacitors 3a, 3b; an electricity controller 12, 37 which comprises first and second regulatory MOS-FETs 10, 35, 12, 37 connected between respectively one and the other ends of a secondary winding 9b, 9c of transformer 9 and a speaker 15, 40; a polarity detector 51 for detecting the polarity of AC voltage produced on secondary winding 9b, 9c of transformer 9 by the on and off operation of MOS-FETs 4, 5 to generate detection signals; and a drive circuit 24, 25, 49, 50 for receiving detection signals from polarity detector 51 to control the on and off operation of first and second regulatory MOS-FETs 10, 35, 11, 36 to simplify the circuit configuration and improve power conversion efficiency in