Patents by Inventor Toshitaka Yamamoto

Toshitaka Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220281830
    Abstract: The present invention relates to a novel salt of 2-(4-(5,6-diphenylpyrazin-2-yl)(isopropyl)amino)butoxy)acetic acid (hereinafter referred to as “Compound B”) and a crystal of the salt thereof.
    Type: Application
    Filed: August 19, 2020
    Publication date: September 8, 2022
    Applicant: NIPPON SHINYAKU CO., LTD.
    Inventors: Yasushi KOKUBO, Toshitaka YAMAMOTO, Koji NAKAMICHI, Domenico CROCCO
  • Patent number: 6963513
    Abstract: The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells of a flash memory are formed in their corresponding chips lying in a wafer. Subsequently, memory information is written into each of the memory cells of the flash ROM in a probe test process. Thereafter, the memory information written into the memory cell thereof is made unreprogrammable to thereby disable rewriting of the post-shipment memory information. Thus, the shortening of a TAT can be achieved as compared with a mask ROM built-in microcomputer, and management and fabrication costs can be reduced.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: November 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshitaka Yamamoto, Shouji Satou
  • Publication number: 20050019972
    Abstract: The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells of a flash memory are formed in their corresponding chips lying in a wafer. Subsequently, memory information is written into each of the memory cells of the flash ROM in a probe test process. Thereafter, the memory information written into the memory cell thereof is made unreprogrammable to thereby disable rewriting of the post-shipment memory information. Thus, the shortening of a TAT can be achieved as compared with a mask ROM built-in microcomputer, and management and fabrication costs can be reduced.
    Type: Application
    Filed: August 17, 2004
    Publication date: January 27, 2005
    Inventors: Toshitaka Yamamoto, Shouji Satou
  • Patent number: 6815322
    Abstract: The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells of a flash memory are formed in their corresponding chips lying in a wafer. Subsequently, memory information is written into each of the memory cells of the flash ROM in a probe test process. Thereafter, the memory information written into the memory cell thereof is made unreprogrammable to thereby disable rewriting of the post-shipment memory information. Thus, the shortening of a TAT can be achieved as compared with a mask ROM built-in microcomputer, and management and fabrication costs can be reduced.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Toshitaka Yamamoto, Shouji Satou
  • Publication number: 20040014283
    Abstract: The present invention provides a technology capable of shortening a TAT of a microcomputer with a nonvolatile memory built therein and achieving a reduction in cost. Flash ROMs comprising memory cells each substantially identical in structure to each of memory cells of a flash memory are formed in their corresponding chips lying in a wafer. Subsequently, memory information is written into each of the memory cells of the flash ROM in a probe test process. Thereafter, the memory information written into the memory cell thereof is made unreprogrammable to thereby disable rewriting of the post-shipment memory information. Thus, the shortening of a TAT can be achieved as compared with a mask ROM built-in microcomputer, and management and fabrication costs can be reduced.
    Type: Application
    Filed: June 10, 2003
    Publication date: January 22, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Toshitaka Yamamoto, Shouji Satou
  • Patent number: 5702228
    Abstract: An arm member having a folding expansion/contraction mechanism is fixed to a rotary shaft. A support member is rotatively mounted on the distal end of the arm member. This support member maintains a constant relationship with the rotary shaft. An auxiliary support member is mounted on a support shaft fixed to the support member, the auxiliary support member being able to swing. A cam mechanism is provided at rotation portions of the support member and auxiliary support member. The auxiliary support member is swung by this cam mechanism in accordance with a folding expansion/contraction motion of the arm member.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: December 30, 1997
    Assignee: Sumitomo Heavy Industries, Ltd.
    Inventors: Tadamoto Tamai, Toshitaka Yamamoto
  • Patent number: 5628022
    Abstract: In a microcomputer with a programmable ROM, there is provided an external pin at which a mode select signal is entered so as to select one of three modes, including a MCU mode in which an application system is controlled by an application program which has been stored in the programmable ROM, a PROM mode in which the application program is written into the programmable ROM, and an inline mode in which predetermined data is written to a part of the programmable ROM with the microcomputer mounted on a user system.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: May 6, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Ueno, Kenichi Ono, Toshitaka Yamamoto
  • Patent number: 4503597
    Abstract: A method of forming a number of discrete solder layers on a semiconductor wafer of a large area. A number of regions which are easy to be wetted with solder are formed on one of the major surfaces of the wafer. A solder foil is positioned on the one major surface and a plate-like jig including a plate and projections formed on one surface thereof is disposed on the solder foil with the projections facing the latter. By heating the stacked assembly at a sufficiently high temperature for the solder foil to be molten, a number of the discrete solder layers having a uniform thickness are formed on the semiconductor wafer.
    Type: Grant
    Filed: February 7, 1983
    Date of Patent: March 12, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Tadao Kushima, Masahiro Gooda, Tasao Soga, Toshitaka Yamamoto