Patents by Inventor Toshitugu Takekuma

Toshitugu Takekuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
    Patent number: 5805513
    Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: September 8, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takekuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura
  • Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
    Patent number: 5426613
    Abstract: A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: June 20, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama, Toshitugu Takekuma, Shigetoshi Sakomura, Kazuyuki Miyazawa, Masamichi Ishihara, Ryoichi Hori, Takeshi Kizaki, Yoshihisa Koyama, Haruo Ii, Masaya Muranaka, Hidetomo Aoyagi, Hiromi Matsuura