Patents by Inventor Toshiya Ishio
Toshiya Ishio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11239395Abstract: An image display device includes: a plurality of LED elements that are mounted on a drive circuit substrate and emit light source light; a wavelength conversion layer that is stacked on a side of the LED elements opposite to the drive circuit substrate, converts the light source light emitted by the LED elements into long wavelength light, and emits the long wavelength light to a side opposite to the drive circuit substrate; and a first functional layer that is disposed on a light emitting surface side of the long wavelength light of the wavelength conversion layer, reflects the light source light, and transmits the long wavelength light.Type: GrantFiled: March 5, 2020Date of Patent: February 1, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Masumi Maegawa, Hitoshi Aoki, Toshiya Ishio, Katsuji Iguchi
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Publication number: 20210135064Abstract: A display device includes a plurality of light-emitting elements, color conversion layers configured to convert a color of light emitted from the plurality of light-emitting elements, and a partition configured to separate a region provided with each of the color conversion layers, wherein the partition is formed of an inorganic material having a light-shielding property.Type: ApplicationFiled: October 29, 2020Publication date: May 6, 2021Inventor: TOSHIYA ISHIO
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Publication number: 20210005520Abstract: A method for manufacturing an array device includes a placing step of providing a plurality of elements in an array on a first surface of a substrate, an element separating step of separating a plurality of element chips from one another so that each element chip includes one or more elements, an inspecting step of inspecting the plurality of elements, a removing step of removing any element chip of the plurality of element chips from the surface of the substrate on the basis of a result of the inspecting step, and a mounting step of, after the removing step, mounting an element of at least the elements other than an element of the element chip thus removed onto a mounting substrate by transfer from the substrate, the mounting substrate being different from the substrate.Type: ApplicationFiled: June 30, 2020Publication date: January 7, 2021Inventors: TOSHIYA ISHIO, HITOSHI AOKI
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Patent number: 10861813Abstract: A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.Type: GrantFiled: May 24, 2019Date of Patent: December 8, 2020Assignee: SHARP KABUSHIKI KAISHAInventor: Toshiya Ishio
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Publication number: 20200287103Abstract: An image display device includes: a plurality of LED elements that are mounted on a drive circuit substrate and emit light source light; a wavelength conversion layer that is stacked on a side of the LED elements opposite to the drive circuit substrate, converts the light source light emitted by the LED elements into long wavelength light, and emits the long wavelength light to a side opposite to the drive circuit substrate; and a first functional layer that is disposed on a light emitting surface side of the long wavelength light of the wavelength conversion layer, reflects the light source light, and transmits the long wavelength light.Type: ApplicationFiled: March 5, 2020Publication date: September 10, 2020Inventors: MASUMI MAEGAWA, HITOSHI AOKI, TOSHIYA ISHIO, KATSUJI IGUCHI
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Publication number: 20190371756Abstract: A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.Type: ApplicationFiled: May 24, 2019Publication date: December 5, 2019Inventor: TOSHIYA ISHIO
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Patent number: 8622594Abstract: A light emitting element module with a high yield where a portion through which a substrate and a lens are bonded can be prevented from cracking and peeling due to thermal expansion is provided. A light emitting element part equipped with a light emitting element and an optical lens for diffusing light from the light emitting element are provided on a substrate in the light emitting element module, where the lens is fixed to the substrate with an adhesive resin having a tensile breaking elongation of 50% or more. The lens also has a plurality of supports and is fixed to the substrate through these supports, so that stress in the portion where the substrate and the lens are bonded can be dispersed between the supports, and a layer in which air can circulate so as to release heat is provided between the substrate and the lens.Type: GrantFiled: July 8, 2010Date of Patent: January 7, 2014Assignee: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Yasuhiko Tanaka
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Patent number: 8297784Abstract: A surface-emission unit to prevent irregularity in brightness from being generated is provided. The surface-emission unit is composed of light-emission element parts each having a light-emission element, aligned and arranged on a substrate two-dimensionally, and optical lenses each arranged on the substrate with respect to each light-emission element part, to diffuse light from the light-emission element, and a support part to fix the optical lens onto the substrate is arranged so as not overlap a line connecting the light-emission element part corresponding to the optical lens fixed by the support part, to another light-emission element part adjacent to the light-emission element part.Type: GrantFiled: July 13, 2010Date of Patent: October 30, 2012Assignee: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Mitsuru Hineno, Nobuo Ogata, Shinji Suminoe
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Patent number: 7906856Abstract: A semiconductor device has a semiconductor chip provided with an insulating layer formed so as to be thinner in a first secondary-wire-free area than in a first secondary-wire-containing area. Further, the semiconductor chip has an edge extending further outward than a side wall, which severs as an edge of an upper insulating layer, in an extending direction of a circuit-forming surface of the semiconductor chip on which electrode pads are provided. This makes it possible to provide a semiconductor device capable of suppressing electromagnetic interference between a secondary wire and an electronic circuit of a semiconductor chip and the curvature of a wafer even in the case of overlap between the secondary wire and the electronic circuit, and of reducing the risk of occurrence of chipping in a dicing step.Type: GrantFiled: April 25, 2008Date of Patent: March 15, 2011Assignee: Sharp Kabushiki KaishaInventor: Toshiya Ishio
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Publication number: 20110013393Abstract: A surface-emission unit to prevent irregularity in brightness from being generated is provided. The surface-emission unit is composed of light-emission element parts each having a light-emission element, aligned and arranged on a substrate two-dimensionally, and optical lenses each arranged on the substrate with respect to each light-emission element part, to diffuse light from the light-emission element, and a support part to fix the optical lens onto the substrate is arranged so as not overlap a line connecting the light-emission element part corresponding to the optical lens fixed by the support part, to another light-emission element part adjacent to the light-emission element part.Type: ApplicationFiled: July 13, 2010Publication date: January 20, 2011Applicant: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Mitsuru Hineno, Nobuo Ogata, Shinji Suminoe
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Publication number: 20110007493Abstract: The invention provides a light emitting element module with a high yield where a portion through which a substrate and a lens are bonded can be prevented from cracking and peeling due to thermal expansion. A light emitting element part equipped with a light emitting element and an optical lens for diffusing light from the light emitting element are provided on a substrate in the light emitting element module, where the lens is fixed to the substrate with an adhesive resin having a tensile breaking elongation of 50% or more. The lens also has a plurality of supports and is fixed to the substrate through these supports, so that stress in the portion where the substrate and the lens are bonded can be dispersed between the supports, and a layer in which air can circulate so as to release heat is provided between the substrate and the lens.Type: ApplicationFiled: July 8, 2010Publication date: January 13, 2011Inventors: Toshiya Ishio, Yasuhiko Tanaka
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Patent number: 7667336Abstract: A semiconductor device provided with a semiconductor chip wherein an electrode pad is formed on a circuit formation surface, includes a first passivation film, which serves as an adhering layer; a second passivation film formed on the first passivation film, for protecting the semiconductor chip from external physical damage; a metal film formed so as to cover at least a first electrode-pad opening section of the first passivation film; and an external connection terminal to connect the electrode pad to an external equipment. A second electrode-pad opening section of the second passivation film is formed so as to expose the first electrode-pad opening section entirely. The second passivation film is formed so as not to be in direct contact with the electrode pad.Type: GrantFiled: August 9, 2007Date of Patent: February 23, 2010Assignee: Sharp Kabushiki KaishaInventor: Toshiya Ishio
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Publication number: 20080272500Abstract: A semiconductor device according to the present invention has a semiconductor chip provided with an insulating layer formed so as to be thinner in a first secondary-wire-free area than in a first secondary-wire-containing area. Further, the semiconductor chip has an edge extending further outward than a side wall, which severs as an edge of an upper insulating layer, in an extending direction of a circuit-forming surface of the semiconductor chip on which electrode pads are provided. This makes it possible to provide a semiconductor device capable of suppressing electromagnetic interference between a secondary wire and an electronic circuit of a semiconductor chip and the curvature of a wafer even in the case of overlap between the secondary wire and the electronic circuit, and of reducing the risk of occurrence of chipping in a dicing step.Type: ApplicationFiled: April 25, 2008Publication date: November 6, 2008Applicant: SHARP KABUSHIKI KAISHAInventor: Toshiya ISHIO
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Patent number: 7445958Abstract: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.Type: GrantFiled: June 26, 2006Date of Patent: November 4, 2008Assignee: Sharp Kabushiki KaishaInventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Publication number: 20080150096Abstract: With respect to the central plane which horizontally cuts a multi-chip module, constituent materials of the same type are disposed in a plane symmetrical manner. Each of an upper structure and a lower structure, which sandwich the central plane which horizontally cuts the multi-chip module, includes a base and electronic components, as the aforesaid constituent materials.Type: ApplicationFiled: December 19, 2007Publication date: June 26, 2008Applicant: SHARP KABUSHIKI KAISHAInventor: Toshiya ISHIO
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Publication number: 20080036086Abstract: A semiconductor device provided with a semiconductor chip wherein an electrode pad is formed on a circuit formation surface, includes a first passivation film, which serves as an adhering layer; a second passivation film formed on the first passivation film, for protecting the semiconductor chip from external physical damage; a metal film formed so as to cover at least a first electrode-pad opening section of the first passivation film; and an external connection terminal to connect the electrode pad to an external equipment. A second electrode-pad opening section of the second passivation film is formed so as to expose the first electrode-pad opening section entirely. The second passivation film is formed so as not to be in direct contact with the electrode pad.Type: ApplicationFiled: August 9, 2007Publication date: February 14, 2008Applicant: Sharp Kabushiki KaishaInventor: Toshiya Ishio
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Publication number: 20060237848Abstract: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.Type: ApplicationFiled: June 26, 2006Publication date: October 26, 2006Inventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Patent number: 7091616Abstract: A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.Type: GrantFiled: June 7, 2002Date of Patent: August 15, 2006Assignee: Sharp Kabushiki KaishaInventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Patent number: 6940175Abstract: A semiconductor device includes (i) spacers between a first electronic component and a second electronic component facing each other, for keeping a distance between the first and second electronic components constant and (ii) combining parts for combining the first electronic component with the second electronic component. The spacers are made of liquid resin material made of thermosetting resin, and the combining parts are made of liquid conductive combining material including metal and thermosetting resin.Type: GrantFiled: June 7, 2002Date of Patent: September 6, 2005Assignee: Sharp Kabushiki KaishaInventors: Yoshihide Iwazaki, Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori
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Patent number: 6921980Abstract: An integrated semiconductor circuit includes a semiconductor chip on which surface a plurality of connection electrodes are formed, a lower insulating layer covering the surface of the semiconductor chip such that the connection electrodes are exposed, a plurality of wiring portions formed on the lower insulating layer, each of the wiring portions being connected to the connection electrode at one end and provided with a component connection portion at the other end, an upper insulating layer covering the wiring portions such that the component connection portions are exposed, and an electronic component connected between different component connection portions.Type: GrantFiled: January 31, 2002Date of Patent: July 26, 2005Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Nakanishi, Toshiya Ishio, Katsunobu Mori