Abstract: An electronic component, including: a first terminal group including a plurality of functional terminals provided along a first side of the electronic component; a second terminal group including a plurality of functional terminals provided along a second side of the electronic component opposing the first side; and an element that is connected to at least one of the functional terminals of the first terminal group and to at least one of the functional terminals of the second terminal group. The first terminal group includes a first dummy terminal in at least one space between the functional terminals of the first terminal group; the second terminal group includes a second dummy terminal in at least one space between the functional terminals of the second terminal group; and the first and second dummy terminals are not connected to any element inside the electronic component.

Abstract: A memory access timing adjustment device according to the present invention includes separate memory interfaces (632A to 632D) each of which is separately connected to a corresponding one of the external memories (2) and which transmits and receives data for memory access, a pattern generating circuit (633) which generates specific pattern data, and a processor (60) which adjusts an access timing by causing a separate memory interface connected to the selected external memory to transmit and receive data to and from the selected external memory multiple times, and by placing a load on the external memories by causing at least one separate memory interface connected to at least one external memory other than the selected external memory to transmit the specific pattern data to the at least one external memory.

Abstract: An electronic component, including: a first terminal group including a plurality of functional terminals provided along a first side of the electronic component; a second terminal group including a plurality of functional terminals provided along a second side of the electronic component opposing the first side; and an element that is connected to at least one of the functional terminals of the first terminal group and to at least one of the functional terminals of the second terminal group. The first terminal group includes a first dummy terminal in at least one space between the functional terminals of the first terminal group; the second terminal group includes a second dummy terminal in at least one space between the functional terminals of the second terminal group; and the first and second dummy terminals are not connected to any element inside the electronic component.

Abstract: In a stream demultiplexing device, a synchronous clock signal is supplied to a header processing unit only when a header is being inputted and processed in the header processing unit, and supplied to a payload processing unit only when a payload is being inputted and processed in the payload processing unit. By such cutting off the synchronous clock signal supply to the header processing unit and the payload processing unit while they are not active, power consumption in the stream demultiplexing device is reduced.

Abstract: A use limit system in which only contents users who have made a viewing contract can decrypt encrypted contents and use the contents.

Abstract: An image data format conversion apparatus comprises: a memory storing image data; a data reading means reading image data from the memory to output it; a format converting means converting the image data output from the data reading means to a predetermined format to output it or making the image data pass through without converting it; a vertical filter vertically interpolating the image data output from the format converting means by filtering operation to output the data or making the image data pass through without interpolating it; a horizontal filter vertically interpolating the image data output from the vertical filter by filtering operation to output the data or making the image data pass through without interpolating it; an image synthesizing means performing logic operation for image data output from the filter, and synthesizing the image data to output it; and an image output means outputting the image data from the image synthesizing means to a designated display unit.