Patents by Inventor Toshiyuki Naka

Toshiyuki Naka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10439038
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 8, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tsuyoshi Oota, Hiroko Nonaka, Asami Gorohmaru, Toshiyuki Naka, Norio Yasuhara
  • Patent number: 10438946
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Oota, Hiroko Nonaka, Asami Gorohmaru, Toshiyuki Naka, Norio Yasuhara
  • Publication number: 20180226487
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.
    Type: Application
    Filed: March 9, 2018
    Publication date: August 9, 2018
    Inventors: Tsuyoshi Oota, Hiroko Nonaka, Asami Gorohmaru, Toshiyuki Naka, Norio Yasuhara
  • Publication number: 20180226397
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.
    Type: Application
    Filed: August 30, 2017
    Publication date: August 9, 2018
    Inventors: Tsuyoshi Oota, Hiroko Nonaka, Asami Gorohmaru, Toshiyuki Naka, Norio Yasuhara
  • Publication number: 20170263716
    Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer on the first nitride semiconductor layer, a source electrode on the second nitride semiconductor layer and spaced from the source electrode, a drain electrode on the second nitride semiconductor layer and spaced from the source electrode, a gate electrode between the drain and source electrodes, an interlayer insulating film on the second nitride semiconductor layer, a first field plate electrode in contact with an upper surface of the second nitride semiconductor layer at a location between the gate and drain electrodes, and a second field plate electrode extending through the interlayer insulating film and connected to the first field plate electrode. An end of the second field plate electrode on the source electrode side is closer to the drain electrode than is an end of the first field plate electrode on the source electrode side.
    Type: Application
    Filed: August 22, 2016
    Publication date: September 14, 2017
    Inventors: Yasunobu SAITO, Toshiyuki NAKA
  • Patent number: 9698141
    Abstract: A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka
  • Patent number: 9621150
    Abstract: According to one embodiment, a semiconductor device includes: a first switching element comprising a heterojunction comprising a first compound semiconductor layer and a second compound semiconductor layer; and a driver which applies a voltage to a gate of the first switching element to control turn-on and turn-off of the first switching element. The driver temporarily increases a gate voltage of the first switching element at a timing when the first switching element is turned on, during a period while the first switching element is on.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Naka
  • Publication number: 20170077925
    Abstract: According to embodiments, a semiconductor device includes a field-effect transistor; a switch; and a controller. The field-effect transistor includes a substrate; a nitride semiconductor layer on the substrate; a drain electrode and a source electrode on the nitride semiconductor layer; and a gate electrode between the drain electrode and the source electrode. The switch switches a potential of the substrate to a plurality of potentials. The controller controls the switch so as to set one potential among the plurality of potentials based on an input to the drain electrode.
    Type: Application
    Filed: March 8, 2016
    Publication date: March 16, 2017
    Inventor: Toshiyuki Naka
  • Publication number: 20170069747
    Abstract: A semiconductor device capable of suppressing current collapse is provided. The semiconductor device includes a substrate, a nitride semiconductor layer on the substrate, and including a first region and a second region having a thickness greater than that of the first region, a source electrode on the first region, a drain electrode on the second region, and a gate electrode on the first region between the source electrode and the drain electrode.
    Type: Application
    Filed: March 7, 2016
    Publication date: March 9, 2017
    Inventors: Yasunobu SAITO, Toshiyuki NAKA, Nobuyuki SATO
  • Publication number: 20170069623
    Abstract: A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.
    Type: Application
    Filed: March 7, 2016
    Publication date: March 9, 2017
    Inventors: Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA
  • Publication number: 20160269024
    Abstract: According to one embodiment, a semiconductor device includes: a first switching element comprising a heterojunction comprising a first compound semiconductor layer and a second compound semiconductor layer; and a driver which applies a voltage to a gate of the first switching element to control turn-on and turn-off of the first switching element. The driver temporarily increases a gate voltage of the first switching element at a timing when the first switching element is turned on, during a period while the first switching element is on.
    Type: Application
    Filed: August 28, 2015
    Publication date: September 15, 2016
    Inventor: Toshiyuki Naka
  • Patent number: 9437728
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: September 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
  • Patent number: 9412825
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
  • Patent number: 9349721
    Abstract: A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: May 24, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Hiroaki Yamashita
  • Publication number: 20160072500
    Abstract: According to one embodiment, a controller includes a processor. The controller is able to control a switching element. The processor changes a gate voltage applied to a gate terminal of the switching element from a first voltage value to a second voltage value, and controls the gate voltage to the first voltage value when a drain current flowing through a drain terminal of the switching element increases.
    Type: Application
    Filed: March 10, 2015
    Publication date: March 10, 2016
    Inventor: Toshiyuki Naka
  • Publication number: 20160043213
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 11, 2016
    Inventors: Wataru SAITO, Syotaro ONO, Toshiyuki NAKA, Shunji TANIUCHI, Miho WATANABE, Hiroaki YAMASHITA
  • Patent number: 9196721
    Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
  • Patent number: 9165922
    Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Takeshi Uchihara, Naoko Yanase, Toshiyuki Naka, Tetsuya Ohno, Tasuku Ono
  • Publication number: 20150263152
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Takako MOTAI
  • Publication number: 20150263101
    Abstract: In one embodiment, a semiconductor device includes a semiconductor chip including a nitride semiconductor layer, and including a control electrode, a first electrode and a second electrode provided on the nitride semiconductor layer. The device further includes a support including a substrate, and including a control terminal, a first terminal and a second terminal provided on the substrate. The semiconductor chip is provided on the support such that the control electrode, the first electrode and the second electrode face the support. The control electrode, the first electrode and the second electrode of the semiconductor chip are electrically connected to the control terminal, the first terminal and the second terminal of the support, respectively.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Shingo Masuko, Takaaki Yasumoto, Naoko Yanase, Miki Yumoto, Masahito Mimura, Yasunobu Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takeshi Uchihara, Tetsuya Ohno, Toshiyuki Naka, Tasuku Ono