Patents by Inventor Toshiyuki Shinozaki

Toshiyuki Shinozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6683332
    Abstract: A Pt alloyed reaction layer is formed under a base ohmic electrode. This alloyed reaction layer extends through a base protective layer so as to reach a base layer. Besides, a Pt alloyed reaction layer is formed under an emitter ohmic electrode. This alloyed reaction layer is formed only within a second emitter contact layer. With this constitution, the manufacturing cost for the HBT can be reduced and successful contact characteristics for the HBT can be obtained.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: January 27, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiyuki Shinozaki, Toshiya Tsukao
  • Patent number: 6410945
    Abstract: A heterojunction bipolar transistor having a ballast resistance layer between an AlGaAs emitter layer and an emitter electrode, wherein the ballast resistance layer comprises n-AlxGa1−XAs, wherein 0<X<1, and a GaAs selective etching layer is provided between the emitter layer and the ballast resistance layer.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: June 25, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Shiota, Toshiyuki Shinozaki, Hideyuki Tsuji, Toshiaki Kinosada
  • Publication number: 20010046747
    Abstract: A Pt alloyed reaction layer is formed under a base ohmic electrode. This alloyed reaction layer extends through a base protective layer so as to reach a base layer. Besides, a Pt alloyed reaction layer is formed under an emitter ohmic electrode. This alloyed reaction layer is formed only within a second emitter contact layer. With this constitution, the manufacturing cost for the HBT can be reduced and successful contact characteristics for the HBT can be obtained.
    Type: Application
    Filed: February 5, 2001
    Publication date: November 29, 2001
    Inventors: Toshiyuki Shinozaki, Toshiya Tsukao
  • Patent number: 5882995
    Abstract: In the case where ohmic electrodes are formed on a semiconductor wafer, first of all, an insulating layer is formed on the semiconductor wafer, then a resist layer is formed on the insulating layer. Next, apertures for forming electrodes are formed in first regions of the resist layer corresponding to regions where the electrodes are formed, while dummy apertures are also formed in a second region of the resist layer in a rest part other than the first regions. Thereafter, the insulating layer is etched using the resist layer as a mask. With the resist layer remaining, electrode material is accumulated on the surface of the semiconductor wafer, and thereafter, the resist layer is removed. As a result, electrodes with desirable ohmic characteristics are stably formed.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: March 16, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hideyuki Tsuji, Toshiyuki Shinozaki
  • Patent number: 5721437
    Abstract: A heterojunction type AlGaAs/GaAs bipolar transistor includes an n-GaAs collector layer, a p.sup.+ -GaAs base layer and an n-Al.sub.x Ga.sub.1-x As emitter layer formed in a stack, and an n-Al.sub.y Ga.sub.1-y As ballast resistance layer formed on the emitter layer. The ballast resistance layer has an Al concentration y in the range of 0<y<0.4, and a resistance higher than that of the emitter layer.
    Type: Grant
    Filed: August 23, 1995
    Date of Patent: February 24, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: John Kevin Twynam, Motoji Yagura, Toshiyuki Shinozaki, Toshiaki Kinosada