Abstract: A memory control device capable of controlling data writing into a buffer memory where the data reproduced from a disk recording medium are stored temporarily is disclosed. The control device comprises a signal generation circuit for generating a stable sync detection signal which is obtained at a normal detection timing of a synchronizing signal in response to a sync detection signal generated by detection of the synchronizing signal inserted in the reproduced data per predetermined data unit. The control device further comprises a data writing controller capable of reading out time base information inserted per predetermined data unit in synchronism with the timing of generation of the stable sync detection signal, and also capable of controlling the data writing into the buffer memory on the basis of the time base information thus read.

Abstract: A memory control device capable of controlling data writing into a buffer memory where the data reproduced from a disk recording medium are stored temporarily is disclosed. The control device comprises a signal generation circuit for generating a stable sync detection signal which is obtained at a normal detection timing of a synchronizing signal in response to a sync detection signal generated by detection of the synchronizing signal inserted in the reproduced data per predetermined data unit. The control device further comprises a data writing controller capable of reading out time base information inserted per predetermined data unit in synchronism with the timing of generation of the stable sync detection signal, and also capable of controlling the data writing into the buffer memory on the basis of the time base information thus read.